Inventor

LEBER PETRA

DE39 patents

⚠️ This page may combine multiple inventors who share the name “LEBER PETRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEBER PETRA

IBM

Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture

Inference based condition code generation

Digit validation check control in instruction execution

Negative zero control in instruction execution

Residue prediction of packed data

Decimal floating point instructions to perform directly on compressed decimal floating point data

Decimal scale and convert and split to hexadecimal floating point instruction

Non-overlapping substring detection within a data element string

Inference based condition code generation

Inference based condition code generation

System and method for storing numbers in first and second formats in a register file

Dynamic algorithm selection

Rounding hexadecimal floating point numbers using binary incrementors

Vector convert hexadecimal floating point to scaled decimal instruction

Condition code anticipator for hexadecimal floating point

Residue prediction of packed data

Repurposed hexadecimal floating point data path

Repurposed hexadecimal floating point data path

Instruction interrupt suppression of overflow exception

Overflow detection for sign-magnitude adders

Residue prediction of packed data

Decimal and binary floating point rounding

Overflow detection for sign-magnitude adders

Decimal and binary floating point rounding

Residue-based checking of a shift operation

Decimal and binary floating point rounding

Floating-point conversion with denormalization

Vector test decimal instruction for validity testing

Verifying the correctness of a leading zero counter

Hexadecimal floating point multiply and add instruction

Efficient checking of a condition code anticipator for a floating point processor and/or unit

Plausibility-driven fault detection in string termination logic for fast exact substring match

Inference based condition code generation

3-stack floorplan for floating point unit

Hexadecimal exponent alignment for binary floating point unit

Decimal and binary floating point arithmetic calculations

Post-silicon configurable instruction behavior based on input operands

BOERSMA MAARTEN J

Supporting multiple formats in a floating point processor

KROENER MICHAEL K

Encoding densely packed decimals