Inventor

NAFFZIGER SAMUEL D

US109 patents

⚠️ This page may combine multiple inventors who share the name “NAFFZIGER SAMUEL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAFFZIGER SAMUEL D

HEWLETT PACKARD CO

Cache memory with reduced access time

Transparent data-triggered pipeline latch

Pulse latch with explicit, logic-enabled one-shot

Delay locked loop driver

System and method for writing to and reading from a memory cell

Dynamic logic gate with relaxed timing requirements and output state holding

2&#39;s complement floating-point multiply accumulate unit

Single-ended read, dual-ended write SCRAM cell

Qualified universal clock buffer circuit for generating high gain, low skew local clock signals

High speed addition using Ling&#39;s equations and dynamic CMOS logic

System and method of determining the noise sensitivity of an integrated circuit

System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption

Asymmetric RAM cell

Distributed decode system and method for improving static random access memory (SRAM) density

Asymmetric ram cell

Selective latch for a domino logic gate

Virtual address bypassing using local page mask

System and method for deskewing synchronous clocks in a very large scale integrated circuit

Method of checking for races in a digital design

Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations

Flexible cache architecture using modular arrays

Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method

System and method utilizing on-chip voltage monitoring to manage power consumption

Method and apparatus for bounding alignment shifts to enable at-speed denormalized result generation in an FMAC

Method of decoupling the high order portion of the addend from the multiply result in an FMAC

HEWLETT PACKARD DEVELOPMENT CO

System and method for dynamically varying a clock signal

Manipulating an integrated circuit clock in response to early detection of an operation known to trigger an internal disturbance

System and method of determining the noise sensitivity characterization for an unknown circuit

System for and method of controlling a VLSI environment

System and method to adjust voltage

Method for adding scan controllability and observability to domino CMOS with low area and delay overhead

Method for controlling critical circuits in the design of integrated circuits

Synchronizing link delay measurement over serial links

System and method to mitigate voltage fluctuations

Method of writing to a memory array using clear enable and column clear signals

Inter-die power manager and power management method

Systems and methods for maintaining performance of an integrated circuit within a working power limit

NAFFZIGER SAMUEL D

System for processor power limit management

Managing current and power in a computing system

Managing multiple operating points for stable virtual frequencies

Mechanism for voltage regulator load line compensation using multiple voltage settings per operating state

Flexible power reporting in a computing system

ADVANCED MICRO DEVICES INC

Voltage droop mitigation through instruction issue throttling

Sampling chip activity for real time power estimation

Low power flip flop through partially gated slave clock

(unassigned)

Static random access memory (SRAM) array central global decoder system and method

INTEL CORP

Scannable zero-catcher and one-catcher circuits for reduced clock loading and power dissipation

BRANOVER ALEXANDER

Method and apparatus for thermal control of processing nodes

GLOBALFOUNDRIES INC

Programmable sample clock for empirical setup time selection

SATHE VISVESH S

Clock driver for frequency-scalable systems

2's complement floating-point multiply accumulate unit

High speed addition using Ling's equations and dynamic CMOS logic