Inventor

CHAPPELL ROBERT S

US34 patents

⚠️ This page may combine multiple inventors who share the name “CHAPPELL ROBERT S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAPPELL ROBERT S

INTEL CORP

Zeroing a cache line

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

Method and apparatus for store dependence prediction

Method and apparatus for store durability and ordering in a persistent memory architecture

Apparatuses and methods for speculative execution side channel mitigation

Apparatuses and methods for a processor architecture

Apparatuses and methods for speculative execution side channel mitigation

System and method for replacement in associative memories using weighted PLRU trees

System, apparatus and method for a hybrid reservation station for a processor

Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit

Apparatuses and methods for a processor architecture

Memory management apparatus and method for managing different page tables for different privilege levels

Microarchitectural mechanisms for the prevention of side-channel attacks

Memory management apparatus and method for managing different page tables for different privilege levels

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Criticality based port scheduling

System and method for replacement in associative memories using weighted PLRU trees

Method and apparatus for approximation using polynomials

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Method and apparatus for bus lock assistance

Method and apparatus for bus lock assistance

Method and apparatus for bus lock assistance

Physical reference list for tracking physical register sharing

Instruction and logic for a cache prefetcher and dataless fill buffer

CHAPPELL ROBERT S

Method and apparatus for bus lock assistance

Hybrid cache state and filter tracking of memory operations during a transaction

HINTON GLENN

Apparatus, method, and system for implementing micro page tables

GOPAL VINODH

Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

HILDESHEIM GUR

Concurrent page table walker control for TLB miss handling

KIM HO-SEOP

Store address prediction for memory disambiguation in a processing device

FANG ZHEN

Cache memory power reduction techniques

DIXON MARTIN G

Systems, apparatuses, and methods for implementing temporary escalated privilege

BAIR MICHAEL S

Regulating atomic memory operations to prevent denial of service attack