Inventor

BROCKMANN RUSSELL C

US26 patents

⚠️ This page may combine multiple inventors who share the name “BROCKMANN RUSSELL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BROCKMANN RUSSELL C

HEWLETT PACKARD CO

Method for processing information in a microprocessor to facilitate debug and performance monitoring

System and method for on-chip debug support and performance monitoring in a microprocessor

Memory-resource-driven arbitration

Speculative execution of test patterns in a random test generator

Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results

Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle

Addressing method and apparatus for a computer system

Flexible N-way memory interleaving

Preservation of priority in computer bus arbitration

Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns

Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system

Methods and apparatus for carrying out transactions in a computer system

Method for enhanced functional testing of a processor using dynamic trap handlers

Input comparison circuitry and method for a programmable state machine

Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for implementing two architectures in a chip

Method and apparatus for verifying the correctness of a processor behavioral model

Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit

Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine

Method and apparatus for testing microarchitectural features by using tests written in microcode

Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition

Method and apparatus to reduce penalty of microcode lookup

Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM

Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information

Method and apparatus for reducing branch prediction table pollution

Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine