P

Inventor

YU ROY

US38 patents

Patents

38 patents
US7354798B2Apr 8, 2008

Three-dimensional device fabrication method

IBM285 citations99
US6599778B2Jul 29, 2003

Chip and wafer integration process using vertical connections

IBM495 citations99
US6864165B1Mar 8, 2005

Method of fabricating integrated electronic chip with an interconnect device

IBM83 citations98
US6600224B1Jul 29, 2003

Thin film attachment to laminate using a dendritic interconnection

IBM83 citations98
US6036809AMar 14, 2000

Process for releasing a thin-film structure from a substrate

IBM112 citations98
US6856025B2Feb 15, 2005

Chip and wafer integration process using vertical connections

IBM35 citations96
US6835589B2Dec 28, 2004

Three-dimensional integrated CMOS-MEMS device and process for making the same

IBM48 citations96
US6444560B1Sep 3, 2002

Process for making fine pitch connections between devices and structure made by the process

IBM65 citations96
US6281452B1Aug 28, 2001

Multi-level thin-film electronic packaging structure and related method

IBM53 citations95
US6183588B1Feb 6, 2001

Process for transferring a thin-film structure to a substrate

IBM52 citations95
US7564118B2Jul 21, 2009

Chip and wafer integration process using vertical connections

IBM23 citations93
US7388277B2Jun 17, 2008

Chip and wafer integration process using vertical connections

IBM20 citations93
US7071031B2Jul 4, 2006

Three-dimensional integrated CMOS-MEMS device and process for making the same

IBM42 citations93
US7049697B2May 23, 2006

Process for making fine pitch connections between devices and structure made by the process

IBM22 citations93
US6737297B2May 18, 2004

Process for making fine pitch connections between devices and structure made by the process

IBM32 citations93
US6640021B2Oct 28, 2003

Fabrication of a hybrid integrated circuit device including an optoelectronic chip

IBM47 citations93
US5458520AOct 17, 1995

Method for producing planar field emission structure

IBM86 citations93
US6678949B2Jan 20, 2004

Process for forming a multi-level thin-film electronic packaging structure

IBM21 citations92
US6339527B1Jan 15, 2002

Thin film capacitor on ceramic

IBM41 citations92
US6143117ANov 7, 2000

Process for transferring a thin-film structure to a temporary carrier

IBM28 citations92
US6090633AJul 18, 2000

Multiple-plane pair thin-film structure and process of manufacture

IBM46 citations92
US6099935AAug 8, 2000

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

IBM24 citations91
US6998327B2Feb 14, 2006

Thin film transfer join process and multilevel thin film module

IBM27 citations88
US5735452AApr 7, 1998

Ball grid array by partitioned lamination process

IBM38 citations87
US6149048ANov 21, 2000

Apparatus and method for use in manufacturing semiconductor devices

IBM7 citations72
US6048741AApr 11, 2000

Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

IBM6 citations71
US6323045B1Nov 27, 2001

Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process

IBM10 citations69
US6331731B1Dec 18, 2001

Column for module component

IBM9 citations66
US5722579AMar 3, 1998

Bottom-surface-metallurgy rework process in ceramic modules

IBM13 citations66
US6235412B1May 22, 2001

Corrosion-resistant terminal metal pads for thin film packages

IBM4 citations62
US6083375AJul 4, 2000

Process for producing corrosion-resistant terminal metal pads for thin film packages

IBM5 citations62
US6448169B1Sep 10, 2002

Apparatus and method for use in manufacturing semiconductor devices

IBM5 citations61
US6455331B2Sep 24, 2002

Process of top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

IBM3 citations60
US6248599B1Jun 19, 2001

Top-surface-metallurgy plate-up bonding and rewiring for multilayer devices

IBM2 citations60
US6054749AApr 25, 2000

Thin film device repaired using enhanced repair process

IBM2 citations60
US5972723AOct 26, 1999

Enhanced thin film wiring net repair process

IBM2 citations60
US5937269AAug 10, 1999

Graphics assisted manufacturing process for thin-film devices

IBM6 citations60
US11959874B2Apr 16, 2024

Nanostructure featuring nano-topography with optimized electrical and biochemical properties

IBM0 citations58