Inventor

AN JUDY XILIN

US46 patents

⚠️ This page may combine multiple inventors who share the name “AN JUDY XILIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AN JUDY XILIN

ADVANCED MICRO DEVICES INC

Narrow fin FinFET

Strained channel FinFET

Method for forming multiple fins in a semiconductor device

Semiconductor device having a U-shaped gate structure

Strained channel finfet

Double spacer FinFET formation

Method for forming multiple structures in a semiconductor device

Method for forming tri-gate FinFET with mesa isolation

FinFET-based SRAM cell

Narrow fin FinFET

Uniformly doped source/drain junction in a double-gate MOSFET

Method for forming channels in a finfet device

Self-aligned floating body control for SOI device through leakage enhanced buried oxide

Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness

Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness

Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer

Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET

Germanium MOSFET devices and methods for making same

Double-gate semiconductor device

Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation.

Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation

MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions

Germanium MOSFET devices and methods for making same

Tri-gate and gate around MOSFET devices and methods for making same

Semiconductor device having a gate structure surrounding a fin

Semiconductor device having a thin fin and raised source/drain areas

Method for forming a gate in a FinFET device

Method and apparatus for making MOSFETs with elevated source/drain extensions

MOS transistor with minimal overlap between gate and source/drain extensions

Method and apparatus for making mosfet&#39;s with elevated source/drain extensions

Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding

FinFET device with multiple channels

Two transistor NOR device

Method of manufacturing a semiconductor device having a fin structure

MOS transistor with stepped gate insulator

Field effect transistor with a buried and confined metal plate to control short channel effects

MOS transistor with stepped gate insulator

Integrated circuit tester information processing system for nonlinear mobility model for strained device

Formation of semiconductor devices to achieve &lt;100&gt; channel orientation

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

LIN MING-REN

Double and triple gate MOSFET devices and methods for making same

Double and triple gate MOSFET devices and methods for making same

ADVANCE MICRO DEVICES INC

Asymmetrical double gate or all-around gate MOSFET devices and methods for making same

Globalfoundries

FinFET device with multiple fin structures

AN JUDY XILIN

Germanium MOSFET devices and methods for making same

GLOBALFOUNDRIES INC

Integrated circuit tester information processing system

Method and apparatus for making mosfet's with elevated source/drain extensions

Formation of semiconductor devices to achieve <100> channel orientation