Inventor

JANG SYUN-MING

TW337 patents

⚠️ This page may combine multiple inventors who share the name “JANG SYUN-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JANG SYUN-MING

TAIWAN SEMICONDUCTOR MFG

High selectivity Si-rich SiON etch-stop layer

Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby

Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby

Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines

Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer

Deposit-etch-deposit ozone/teos insulator layer method

Method for forming dummy structures for improved CMP and reduced capacitance

Method for forming a carbon doped oxide low-k insulating layer

Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material

Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer

Method of forming a semiconductor device with multiple thickness gate dielectric layers

Two-stage Cu anneal to improve Cu damascene process

Use of stop layer for chemical mechanical polishing of CU damascene

Method of photo alignment for shallow trench isolation chemical-mechanical polishing

Robust end-point detection for contact and via etching

Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers

Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer

Method of achieving improved STI gap fill with reduced stress

SiOCH low k surface protection layer formation by CxHy gas plasma treatment

Lining and corner rounding method for shallow trench isolation

Methods to improve copper-fluorinated silica glass interconnects

Method of making transistor with strained source/drain

Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion

Slurry dispenser having multiple adjustable nozzles

Fabrication of MIM capacitor in copper damascene process

Method for reducing gate oxide effective thickness and leakage current

Solution to black diamond film delamination problem

Method for improvement of planarity of electroplated copper

Dual damascene method employing spin-on polymer (SOP) etch stop layer

High selectivity Si-rich SiON etch-stop layer

Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish

Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials

Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS

Dual damascene patterned conductor layer formation method without etch stop layer

Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer

Method of enclosing copper conductor in a dual damascene process

Top metal and passivation procedures for copper damascene structures

Readable alignment mark structure formed using enhanced chemical mechanical polishing

Dual damascene patterned conductor layer formation method without etch stop layer

Method for alignment mark regeneration

Trench filling method employing silicon liner layer and gap filling silicon oxide trench fill layer

Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration

Shallow trench isolation method

Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing

Self-aligned sacrificial oxide for shallow trench isolation

Gap-filling of O3 -TEOS for shallow trench isolation

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

TAIWAN SEMICONDUCTOR MANFACTUR

Method to reduce via poison in low-k Cu dual damascene by UV-treatment

TAIWAN SEMICONDUCTOR MAUFACTUR

Shallow trench isolation filled by high density plasma chemical vapor deposition

TAIWAN SEMICONDCUTOR MFG COMPA

Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process