Inventor

HUANG MAO-LIN

TW97 patents

⚠️ This page may combine multiple inventors who share the name “HUANG MAO-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG MAO-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

FinFET structures and methods of forming the same

Semiconductor structures and methods thereof

Tuning threshold voltage in nanosheet transitor devices

Gate patterning process for multi-gate devices

Etching back and selective deposition of metal gate

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Input/output semiconductor devices

Semiconductor device with dummy fin and liner and method of forming the same

Mixed workfunction metal for nanosheet device

Etching back and selective deposition of metal gate

Source/drain regions for high electron mobility transistors (HEMT) and methods of forming same

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

Semiconductor device fabrication methods and structures thereof

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

Fin-based semiconductor device structure including self-aligned contacts and method for forming the same

Gate-all-around devices having self-aligned capping between channel and backside power rail

Nanosheet device architecture for cell-height scaling

Semiconductor device structure and methods of forming the same

Semiconductor device fabrication methods and structures thereof

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Self-aligned backside source contact structure

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Integrated circuit including dipole incorporation for threshold voltage tuning in transistors

Work function design to increase density of nanosheet devices

Dipole patterning for CMOS devices

Semiconductor structures and methods thereof

Semiconductor arrangement and method of manufacture

Gate-all-around devices having self-aligned capping between channel and backside power rail

Field effect transistor and method

P-metal gate first gate replacement process for multigate devices

Semiconductor device structure and method for forming the same

Nanosheet device with dipole dielectric layer and methods of forming the same

Gate structure and patterning method

Work function design to increase density of nanosheet devices

Methods of fabricating semiconductor devices for tightening spacing between nanosheets in GAA structures and structures formed thereby

Semiconductor arrangement and method of manufacture

Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby

Tuning threshold voltage in nanosheet transitor devices

Input/output semiconductor devices

Fluorine incorporation method for nanosheet

Device having a gate electrode wrapping around semiconductor layers and proximate to a dielectric fin

Semiconductor device fabrication methods and structures thereof

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Integrated circuit including dipole incorporation for threshold voltage tuning in transistors

FinFET devices and methods of forming the same

P-metal gate first gate replacement process for multigate devices

Field effect transistor and method

Field effect transistor and method

Semiconductor structures and methods thereof

TAIWAN SEMICONDUCTOR MFG

Nanowire MOSFET with support structures for source and drain