Inventor

REDDY CHITRANJAN N

US52 patents

⚠️ This page may combine multiple inventors who share the name “REDDY CHITRANJAN N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REDDY CHITRANJAN N

ALLIANCE SEMICONDUCTOR CORP

DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

Shared memory graphics accelerator system

Synchronous static random access memory having asynchronous test mode

Hierarchical redundancy scheme for high density monolithic memories

Semiconductor devices having cooperative mode option at assembly stage and method thereof

Shared memory graphics accelerator system

Highly integrated low voltage SRAM array with low resistance Vss lines

Staggered pipeline access scheme for synchronous random access memory

Random access memory word line select circuit having rapid dynamic deselect

Semiconductor devices having cooperative mode option at assembly stage and method thereof

Random access memory with fast, compact sensing and selection architecture

Redundancy scheme for monolithic memories

Monolithic fail bit memory

High speed/low speed interface with prediction cache

Laser fusible link structure for semiconductor devices

Random access memory having selective intra-bank fast activation of sense amplifiers

Reduced area word line driving circuit for random access memory

Burst random access memory employing sequenced banks of local tri-state drivers

Timing control circuit for synchronous static random access memory

Dual-port random access memory having reduced architecture

Random access memory redundancy circuit employing fusible links

Flash EPROM array with self-aligned source contacts and programmable sector erase architecture

DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

Apparatus and method of reducing the pre-charge time of bit lines in a random access memory

Data sense arrangement for random access memory

High performance random access memory with multiple local I/O lines

Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures

Shared memory graphics accelerator system

Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures

Staggered pipeline access scheme for synchronous random access memory

Dynamic random access memory cell having increased capacitance

Pre-sense amplifier for monolithic memories

Fusible link structure for semiconductor devices

High-speed address transition detection circuit

High speed and hierarchical address transition detection circuit

Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current

TEXAS INSTRUMENTS INC

Dynamic memory with high speed nibble mode

Reduction of gate oxide breakdown for booted nodes in MOS integrated circuits

Self refresh circuitry for dynamic memory

High-speed low-power delayed clock generator

Sequentially clocked substrate bias generator for dynamic memory

ACTIVE OPTICAL NETWORKS INC

MEMS devices monolithically integrated with drive and control circuitry

Light modulator with integrated drive and control circuitry

REDDY CHITRANJAN N

Differential latch sense amplifier

Boot-strapped decoder circuit

ALLIANCE SEMICONDUCTORS CORP

Semiconductor electrode having improved grain structure and oxide growth properties

ACTIVE OPTICAL MEMS INC

Light modulator with integrated drive and control circuitry

TUNDRA SEMICONDUCTOR CORP

Integrated high speed switch router using a multiport architecture

(unassigned)

Segmented bus architecture for improving speed in integrated circuit memories