P

Inventor

HALLER WILHELM

DE28 patents
⚠️ This page may combine multiple inventors who share the name “HALLER WILHELM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

22 patents
US5964845AOct 12, 1999

Processing system having improved bi-directional serial clock communication circuitry

IBM18 citations83
US9058456B2Jun 16, 2015

Method and system to fix early mode slacks in a circuit design

IBM11 citations82
US6292819B1Sep 18, 2001

Binary and decimal adder unit

IBM19 citations80
US5928319AJul 27, 1999

Combined binary/decimal adder unit

IBM13 citations73
US5138707AAug 11, 1992

Method of operating a timer in a digital data processing system

IBM12 citations73
US10031995B2Jul 24, 2018

Detecting circuit design flaws based on timing analysis

IBM2 citations72
US7095252B2Aug 22, 2006

Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates

IBM7 citations71
US5634047AMay 27, 1997

Method for executing branch instructions by processing loop end conditions in a second processor

IBM11 citations71
US5944772AAug 31, 1999

Combined adder and logic unit

IBM6 citations62
US7530038B2May 5, 2009

Method and placement tool for designing the layout of an electronic circuit

IBM5 citations61
US5978957ANov 2, 1999

Very fast pipelined shifter element with parity prediction

IBM3 citations61
US8701059B2Apr 15, 2014

Method and system for repartitioning a hierarchical circuit design

IBM3 citations60
US7546565B2Jun 9, 2009

Method for comparing two designs of electronic circuits

IBM2 citations60
US7224190B2May 29, 2007

Midcycle latch for power saving and switching reduction

IBM4 citations60
US5875123AFeb 23, 1999

Carry-select adder with pre-counting of leading zero digits

IBM6 citations60
US7908308B2Mar 15, 2011

Carry-select adder structure and method to generate orthogonal signal levels

IBM5 citations58
US10317465B2Jun 11, 2019

Integrated circuit chip and a method for testing the same

IBM0 citations51
US10006965B2Jun 26, 2018

Integrated circuit chip and a method for testing the same

IBM0 citations51
US9506986B2Nov 29, 2016

Integrated circuit chip and a method for testing the same

IBM1 citations51
US7406495B2Jul 29, 2008

Adder structure with midcycle latch for power reduction

IBM1 citations51
US10528323B2Jan 7, 2020

Circuit for addition of multiple binary numbers

IBM0 citations50
US10168991B2Jan 1, 2019

Circuit for addition of multiple binary numbers

IBM0 citations50

GAUGLER ELMAR

2 patents

HALLER WILHELM

2 patents

DAELLENBACH LUKAS

1 patent

WETTER HOLGER

1 patent