Inventor

CHU JACK O

US75 patents

⚠️ This page may combine multiple inventors who share the name “CHU JACK O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHU JACK O

IBM

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing

Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications

Strained Si based layer made by UHV-CVD, and devices therein

Low temperature emitter process for high performance bipolar devices

Capacitors with roughened single crystal plates

Method of creating defect free high Ge content (&gt;25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector

High performance strained silicon FinFETs device and method for forming same

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate

Thin film wafer transfer and structure for electronic devices

Nanowire MOSFET with doped epitaxial contacts for source and drain

Suspended germanium photodetector for silicon waveguide

Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector

Single reactor, multi-pressure chemical vapor deposition for semiconductor devices

Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen

Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned COSI2 on raised source drain Si/SiGe device

Heteroepitaxial growth of germanium on silicon by UHV/CVD

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Nanowire field effect transistor (FET) and method for fabricating the same

Integrated circuit tamper detection and response

Carbon nanostructure device fabrication utilizing protect layers

Structure for and method of fabricating a high-mobility field-effect transistor

Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device

Low temperature selective growth of silicon or silicon alloys

CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode

High speed GE channel heterostructures for field effect devices

Structure for and method of fabricating a high-mobility field-effect transistor

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Thin film wafer transfer and structure for electronic devices

Selective and conformal passivation layer for 3D high-mobility channel devices

Nanowire field effect transistor (FET) and method for fabricating the same

Carbon nanostructure device fabrication utilizing protect layers

Method to increase carbon and boron doping concentrations in Si and SiGe films

Method of creating defect free high Ge content (&gt;25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (&gt; 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications

Nonselective germanium deposition by UHV/CVD

Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate

CHU JACK O

Graphene growth on a carbon-containing semiconductor layer

Graphene growth on a non-hexagonal lattice

Formation of a graphene layer on a large substrate

Method and apparatus for fabricating a heterojunction bipolar transistor

ASSEFA SOLOMON

Suspended germanium photodetector for silicon waveguide

BOL AGEETH A

Graphene formation utilizing solid phase carbon sources

TYBERG CHRISTY S

BEOL compatible FET structrure

GLOBALFOUNDRIES INC

Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact

Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques