Inventor
SMITH RICHARD PETER
US25 patents
⚠️ This page may combine multiple inventors who share the name “SMITH RICHARD PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CREE INC
18 patentsUS8049252B2Nov 1, 2011
Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices
CREE INC124 citations99
US7906799B2Mar 15, 2011
Nitride-based transistors with a protective layer and a low-damage recess
CREE INC122 citations99
US7709269B2May 4, 2010
Methods of fabricating transistors including dielectrically-supported gate electrodes
CREE INC128 citations99
US7238560B2Jul 3, 2007
Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
CREE INC145 citations99
US7045404B2May 16, 2006
Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
CREE INC184 citations99
US6982204B2Jan 3, 2006
Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
CREE INC205 citations99
US6777278B2Aug 17, 2004
Methods of fabricating aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
CREE INC146 citations99
US6548333B2Apr 15, 2003
Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
CREE INC408 citations99
US7709859B2May 4, 2010
Cap layers including aluminum nitride for nitride-based transistors
CREE INC108 citations98
US7678628B2Mar 16, 2010
Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
CREE INC73 citations98
US7550784B2Jun 23, 2009
Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
CREE INC75 citations98
US7465967B2Dec 16, 2008
Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
CREE INC94 citations98
US7456443B2Nov 25, 2008
Transistors having buried n-type and p-type regions beneath the source region
CREE INC80 citations98
US7432142B2Oct 7, 2008
Methods of fabricating nitride-based transistors having regrown ohmic contact regions
CREE INC116 citations98
US7332795B2Feb 19, 2008
Dielectric passivation for semiconductor devices
CREE INC94 citations98
US7525122B2Apr 28, 2009
Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
CREE INC22 citations92
US7858460B2Dec 28, 2010
Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
CREE INC10 citations83
US9224596B2Dec 29, 2015
Methods of fabricating thick semi-insulating or insulating epitaxial gallium nitride layers
CREE INC1 citations52
SAXLER ADAM WILLIAM
3 patentsUS8575651B2Nov 5, 2013
Devices having thick semi-insulating epitaxial gallium nitride layer
SAXLER ADAM WILLIAM3 citations63
US9166033B2Oct 20, 2015
Methods of passivating surfaces of wide bandgap semiconductor devices
SAXLER ADAM WILLIAM1 citations52
US8946777B2Feb 3, 2015
Nitride-based transistors having laterally grown active region and methods of fabricating same
SAXLER ADAM WILLIAM0 citations42
SMITH RICHARD PETER
2 patentsUS8212289B2Jul 3, 2012
Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
SMITH RICHARD PETER5 citations71
US8803198B2Aug 12, 2014
Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
SMITH RICHARD PETER1 citations60