Inventor

JOSHI RAJEEV

US65 patents

⚠️ This page may combine multiple inventors who share the name “JOSHI RAJEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOSHI RAJEEV

FAIRCHILD SEMICONDUCTOR

Substrate based unmolded package including lead frame structure and semiconductor die

High performance multi-chip flip chip package

Thin, thermally enhanced flip chip in a leaded molded package

High performance multi-chip flip chip package

Semiconductor die including conductive columns

High performance multi-chip flip package

Semiconductor die package with improved thermal and electrical performance

High performance multi-chip flip chip package

Unmolded package for a semiconductor device

High performance flip chip package

Lead frame structure with aperture or groove for flip chip in a leaded molded package

Method for making a semiconductor die package

Lead frame structure with aperture or groove for flip chip in a leaded molded package

Structure of integrated trace of chip package

Multichip module including substrate with an array of interconnect structures

Wafer-level coated copper stud bumps

Flip chip in leaded molded package and method of manufacture thereof

Dual metal stud bumping for flip chip applications

Flip chip in leaded molded package and method of manufacture thereof

Surface mount multi-channel optocoupler

Flip chip in leaded molded package and method of manufacture thereof

Thin, thermally enhanced molded package with leadframe having protruding region

Method to manufacture a universal footprint for a package with exposed chip

Flip chip in leaded molded package with two dies

Passivation scheme for bumped wafers

Surface mountable optocoupler package

Semiconductor die package and method for making the same

Semiconductor die package including multiple dies and a common node structure

High performance multi-chip flip chip package

Substrate based unmolded package

Flip chip in leaded molded package with two dies

Unmolded package for a semiconductor device

Multi-flip chip on lead frame on over molded IC package and method of assembly

Flip chip in leaded molded package and method of manufacture thereof

Flip chip substrate design

Method of assembly for multi-flip chip on lead frame on overmolded IC package

Passivation scheme for bumped wafers

Flip chip substrate design

Thin, thermally enhanced flip chip in a leaded molded package

NAT SEMICONDUCTOR CORP

Thermally enhanced micro-ball grid array package

Carrier based IC packaging arrangement

Method for making a carrier based IC packaging arrangement

DC/DC converter power module package incorporating a stacked controller and construction methodology

JOSHI RAJEEV

Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein

Leadframe based magnetics package

JEON OSEOB

Semiconductor die package and method for making the same

Semiconductor die package and method for making the same

(unassigned)

High performance flip chip package

FAIRCHILD SEMICONDCUTOR CORP

Substrate based unmolded package

FAIRCHILD KR SEMICONDUCTOR LTD

Wafer-level chip scale package and method for fabricating and using the same