Inventor

WINOGRAD GIL I

US58 patents

⚠️ This page may combine multiple inventors who share the name “WINOGRAD GIL I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WINOGRAD GIL I

BROADCOM CORP

Refresh techniques for memory data retention

Synchronous global controller for enhanced pipelining

Synchronous global controller for enhanced pipelining

Programmable refresh scheduler for embedded DRAMs

Synchronous controlled, self-timed local SRAM block

Programmable refresh scheduler for embedded DRAMs

System and method for controlling logical value and integrity of data in memory systems

Block redundancy implementation in hierarchical rams

Efficent column redundancy techniques

Block redundancy implementation in heirarchical RAM&#39;S

Burn in system and method for improved memory reliability

Synchronous global controller for enhanced pipelining

Synchronous global controller for enhanced pipelining

Synchronous controlled, self-timed local SRAM block

Hardware and software programmable fuses for memory repair

Synchronous controlled, self-timed local SRAM block

Synchronous controlled, self-timed local SRAM block

Hardware and software programmable fuses for memory repair

Sense amplifier with adaptive reference generation

Bus twisting scheme for distributed coupling and low power

Distributed, highly configurable modular predecoding

Block redundancy implementation in heirarchical RAM&#39;s

Memory architecture with local and global control circuitry

Memory architecture with local and global control circuitry

Burn in system and method for improved memory reliability

Sense amplifier with adaptive reference generation

Non-volatile memory cell techniques

Sense amplifier with adaptive reference generation

Efficient column redundancy techniques

Block redundancy implementation in heirarchical ram&#39;s

Distributed, highly configurable modular predecoding

Non-volatile memory apparatus and method capable of controlling the quantity of charge stored in memory cells

NOVELICS LLC

Single-poly non-volatile memory cell

One-time-programmable memory

Integrated circuits with reduced leakage current

Low-power CAM cell

DRAM density enhancements

Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer

Decoder with memory

Leakage control

Efficient sense command generation

Block-by-block leakage control and interface

DRAM architecture

Efficient XOR calculation

DRAM with reduced power consumption

Single-poly non-volatile memory cell

Hybrid DRAM

MENTOR GRAPHICS CORP

NOR-OR decoder

NOVELIES LLC

Memory row and column redundancy

ANVAR ALI

Synchronous global controller for enhanced pipelining

Block redundancy implementation in heirarchical RAM'S

Block redundancy implementation in heirarchical RAM's

Block redundancy implementation in heirarchical ram's