Inventor

WANG HAITING

US133 patents

⚠️ This page may combine multiple inventors who share the name “WANG HAITING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG HAITING

GLOBALFOUNDRIES INC

Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices

Gate cut method

Fin-type field effect transistors with single-diffusion breaks and method

Methods of forming source/drain contact structures on integrated circuit products

Contacts formed with self-aligned cuts

Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology

Integrated circuits having replacement gate structures and methods for fabricating the same

Gate cut method

Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

Insulating gate separation structure and methods of making same

Silicon liner for STI CMP stop in FinFET

Methods of facilitating fabricating transistors

Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology

Fabricating transistor(s) with raised active regions having angled upper surfaces

STI inner spacer to mitigate SDB loading

IC structure with air gap adjacent to gate structure and methods of forming same

Gate contact and cross-coupling contact formation

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Hybrid fin cut with improved fin profiles

Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products

Performing concurrent diffusion break, gate and source/drain contact cut etch processes

Scaled memory structures or other logic devices with middle of the line cuts

Field-effect transistors with fins formed by a damascene-like process

Fin-type field effect transistors with single-diffusion breaks and method

Asymmetric overlay mark for overlay measurement

Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same

Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts

Semiconductor device with reduced parasitic capacitance

Methods, apparatus, and manufacturing system for FinFET devices with reduced parasitic capacitance

Integrated single diffusion break

GLOBALFOUNDRIES US INC

Fin-based lateral bipolar junction transistor with reduced base resistance and method

Single fin structures

Single fin structures

Multiple patterning with self-alignment provided by spacers

Air gap regions of a semiconductor device

Multi-channel replacement metal gate device

Fin on silicon-on-insulator

Single fin structures

Transistor comprising an air gap positioned adjacent a gate electrode

Transistors with multiple silicide layers

Field effect transistor with vertical nanowire in channel region and bottom spacer between the vertical nanowire and gate dielectric material

Lateral bipolar transistor

Gate structures

Lateral bipolar transistor structure with base layer of varying horizontal width and methods to form same

Lateral bipolar transistor

Lateral bipolar transistor

FUNG KA-HING

Self-aligned two-step STI formation through dummy poly removal

HUANG LI-PING

Dummy structure for isolating devices in integrated circuits

BEIJING MICROLIVE VISION TECH CO LTD

Method and apparatus for capturing video, electronic device and computer-readable storage medium

TAIWAN SEMICONDUCTOR MFG

Strained semiconductor device with recessed channel