Inventor

THOMPSON DAVID MATTHEW

US78 patents

⚠️ This page may combine multiple inventors who share the name “THOMPSON DAVID MATTHEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEXAS INSTRUMENTS INC

40 patents

US12019514B2Jun 25, 2024

Handling non-correctable errors

TEXAS INSTRUMENTS INC3 citations86

US11487616B2Nov 1, 2022

Write control for read-modify-write operations in cache memory

TEXAS INSTRUMENTS INC5 citations84

US11416334B2Aug 16, 2022

Handling non-correctable errors

TEXAS INSTRUMENTS INC5 citations84

US11249842B2Feb 15, 2022

Error correcting codes for multi-master memory controller

TEXAS INSTRUMENTS INC4 citations84

US11237905B2Feb 1, 2022

Pipelined read-modify-write operations in cache memory

TEXAS INSTRUMENTS INC5 citations84

US11194617B2Dec 7, 2021

Merging data for write allocate

TEXAS INSTRUMENTS INC6 citations84

US9268708B2Feb 23, 2016

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

TEXAS INSTRUMENTS INC3 citations84

US11816032B2Nov 14, 2023

Cache size change

TEXAS INSTRUMENTS INC2 citations83

US11294707B2Apr 5, 2022

Global coherence operations

TEXAS INSTRUMENTS INC4 citations83

US11307987B2Apr 19, 2022

Tag update bus for updated coherence state

TEXAS INSTRUMENTS INC3 citations82

US12505015B2Dec 23, 2025

Pipelined read-modify-write operations in cache memory

TEXAS INSTRUMENTS INC1 citations74

US9575901B2Feb 21, 2017

Programmable address-based write-through cache control

TEXAS INSTRUMENTS INC1 citations74

US12321270B2Jun 3, 2025

Hardware coherence for memory controller

TEXAS INSTRUMENTS INC0 citations73

US12197331B2Jan 14, 2025

Hardware coherence signaling protocol

TEXAS INSTRUMENTS INC0 citations73

US12135646B2Nov 5, 2024

Cache coherence shared state suppression

TEXAS INSTRUMENTS INC0 citations73

US11789868B2Oct 17, 2023

Hardware coherence signaling protocol

TEXAS INSTRUMENTS INC0 citations73

US11768733B2Sep 26, 2023

Error correcting codes for multi-master memory controller

TEXAS INSTRUMENTS INC2 citations73

US11714754B2Aug 1, 2023

Shadow caches for level 2 cache controller

TEXAS INSTRUMENTS INC0 citations73

US11687457B2Jun 27, 2023

Hardware coherence for memory controller

TEXAS INSTRUMENTS INC0 citations73

US11675700B2Jun 13, 2023

Cache coherence shared state suppression

TEXAS INSTRUMENTS INC0 citations73

US11609818B2Mar 21, 2023

Pipelined read-modify-write operations in cache memory

TEXAS INSTRUMENTS INC2 citations73

US11243883B2Feb 8, 2022

Cache coherence shared state suppression

TEXAS INSTRUMENTS INC0 citations73

US11138117B2Oct 5, 2021

Memory pipeline control in a hierarchical memory system

TEXAS INSTRUMENTS INC2 citations73

US11106584B2Aug 31, 2021

Hardware coherence for memory controller

TEXAS INSTRUMENTS INC1 citations73

US11106583B2Aug 31, 2021

Shadow caches for level 2 cache controller

TEXAS INSTRUMENTS INC1 citations73

US12271314B2Apr 8, 2025

Cache size change

TEXAS INSTRUMENTS INC0 citations72

US11314644B2Apr 26, 2022

Cache size change

TEXAS INSTRUMENTS INC0 citations72

US10642742B2May 5, 2020

Prefetch management in a hierarchical cache system

TEXAS INSTRUMENTS INC1 citations72

US10489305B1Nov 26, 2019

Prefetch kill and revival in an instruction cache

TEXAS INSTRUMENTS INC3 citations72

US12056051B2Aug 6, 2024

Tag update bus for updated coherence state

TEXAS INSTRUMENTS INC1 citations71

US11144456B2Oct 12, 2021

Hardware coherence signaling protocol

TEXAS INSTRUMENTS INC1 citations71

US12517830B2Jan 6, 2026

Write streaming with cache write acknowledgment in a processor

TEXAS INSTRUMENTS INC0 citations63

US12461775B2Nov 4, 2025

Controller with caching and non-caching modes

TEXAS INSTRUMENTS INC0 citations63

US12373286B2Jul 29, 2025

Handling non-correctable errors

TEXAS INSTRUMENTS INC0 citations63

US12332790B2Jun 17, 2025

Multi-level cache security

TEXAS INSTRUMENTS INC0 citations63

US12197332B2Jan 14, 2025

Memory pipeline control in a hierarchical memory system

TEXAS INSTRUMENTS INC0 citations63

US12147301B2Nov 19, 2024

Parallelized scrubbing transactions

TEXAS INSTRUMENTS INC0 citations63

US12045644B2Jul 23, 2024

Pseudo-random way selection

TEXAS INSTRUMENTS INC0 citations63

US12038840B2Jul 16, 2024

Multi-level cache security

TEXAS INSTRUMENTS INC0 citations63

US12014206B2Jun 18, 2024

Pipeline arbitration

TEXAS INSTRUMENTS INC0 citations63

THOMPSON DAVID MATTHEW

7 patents

USD737251SAug 25, 2015

Pair of headphones

THOMPSON DAVID MATTHEW68 citations96

USD721354SJan 20, 2015

Pair of headphones

THOMPSON DAVID MATTHEW50 citations96

USD719548SDec 16, 2014

Pair of headphones

THOMPSON DAVID MATTHEW81 citations96

USD718745SDec 2, 2014

Pair of headphones

THOMPSON DAVID MATTHEW45 citations93

USD718744SDec 2, 2014

Pair of headphones

THOMPSON DAVID MATTHEW36 citations93

USD718283SNov 25, 2014

Pair of earbuds for headphones

THOMPSON DAVID MATTHEW42 citations93

US8091860B2Jan 10, 2012

Valve with sensor

THOMPSON DAVID MATTHEW56 citations92

CHACHAD ABHIJEET ASHOK

1 patent

US9009408B2Apr 14, 2015

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

CHACHAD ABHIJEET ASHOK5 citations92

SEA TO SUMMIT PTY LTD

1 patent

USD625993SOct 26, 2010

Packaging

SEA TO SUMMIT PTY LTD8 citations81

TYSON ROLAND WESLEY

1 patent

USD662355SJun 26, 2012

Tableware

TYSON ROLAND WESLEY10 citations77

Showing the top 50 of 78 patents by PatentIndex Score.