Inventor

SU YI-NIEN

TW45 patents

⚠️ This page may combine multiple inventors who share the name “SU YI-NIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SU YI-NIEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor methods and devices

Semiconductor interconnect structure with bottom self-aligned via landing

Method of forming a semiconductor device

Patterning method for semiconductor device and structures resulting therefrom

Semiconductor methods and devices

Patterning material including silicon-containing layer and method for semiconductor device fabrication

Method of forming a semiconductor device

Patterning material including silicon-containing layer and method for semiconductor device fabrication

Integrated circuit and method for manufacturing the same

Method of manufacturing semiconductor devices

Middle-of-line interconnect structure having air gap and method of fabrication thereof

Lithography method to reduce spacing between interconnect wires in interconnect structure

Method of manufacturing semiconductor devices

Method of forming a semiconductor device

Lithography method to reduce spacing between interconnect wires in interconnect structure

Middle-of-line interconnect structure having air gap and method of fabrication thereof

Integrated circuit and method for manufacturing the same

Method for manufacturing semiconductor structure

Method of forming a semiconductor device

Fin field effect transistor and method of forming the same

Semiconductor devices and methods of manufacture thereof

Method for forming semiconductor structure

Method for reducing line end spacing and semiconductor devices manufactured thereof

Self-aligned via formation using spacers

Methods for fabricating semiconductor structures

Air spacer surrounding conductive features and method forming same

Semiconductor methods and devices

Method for forming semiconductor structure

TAIWAN SEMICONDUCTOR MFG

Air gap interconnect structure and method thereof

Dual damascene structure formed of low-k dielectric materials

Dry-wet-dry solvent-free process after stop layer etch in dual damascene process

Interconnect structure and method of forming the same

Semiconductor devices and methods of manufacture thereof

Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof

Low oxygen content photoresist stripping process for low dielectric constant materials

Method for improved plasma etching control

Method of making dual damascene with via etch through

Method for photoresist stripping and treatment of low-k dielectric material

Interconnect structure and method of forming the same

Damascene gap structure

Contact hole structures and contact structures and fabrication methods thereof

Via structures and trench structures and dual damascene structures

Measuring low dielectric constant film properties during processing

HSU JU-WANG

Fin field effect transistor and method of forming the same

SU YI-NIEN

Dual damascene interconnect in hybrid dielectric