Inventor

MUKESH SAGARIKA

US25 patents

⚠️ This page may combine multiple inventors who share the name “MUKESH SAGARIKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUKESH SAGARIKA

IBM

Backside power rails and power distribution network for density scaling

Topological qubit device

Partial subtractive supervia enabling hyper-scaling

Buried power rail after replacement metal gate

Forksheet transistor with dual depth late cell boundary cut

Self-aligned backside contact integration for transistors

Dual inner spacer epitaxy in monolithic stacked FETs

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

Structurally stable self-aligned subtractive vias

Double patterned microcooler having alternating fin widths

Circuit interconnect structure

Via to backside power rail through active region

Selective patterning of vias with hardmasks

Selective patterning of vias with hardmasks

High aspect ratio buried power rail metallization

Magnetic electrode cochlear implant with in-situ stimulation adjustments

Conformal dielectric cap for subtractive vias

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Stream alterations under limited bandwidth conditions

Self-aligned backside gate contact

Self-aligned top vias over metal lines formed by a damascene process

Stacked FETS with contact placeholder structures

Multilayer dielectric stack for damascene top-via integration

INT BUSINESS MACHINES CORPORATION

Front end of line processing compatible thermally stable buried power rails

TAIWAN SEMICONDUCTOR MFG CO LTD

Correcting disruption of a network during a virtual meeting