Inventor

STEPHENS NIGEL JOHN

GB34 patents

⚠️ This page may combine multiple inventors who share the name “STEPHENS NIGEL JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEPHENS NIGEL JOHN

ADVANCED RISC MACH LTD

Apparatus and method for performing a splice of vectors based on location and length data

Data structure processing

Determine whether to fuse move prefix instruction and immediately following instruction independently of detecting identical destination registers

Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction

Vector arithmetic and logical instructions performing operations on different first and second data element widths from corresponding first and second vector registers

Handling exceptional conditions for vector arithmetic instruction

Data processing

Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers

Register addressing information for data transfer instruction

Data structure relinquishing

Anchored data element conversion

Testing bit values inside vector elements

Data processing

Vector add-with-carry instruction

Vector interleaving in a data processing apparatus

Contingent load suppression

Conditional selection of data elements

Address generation in a data processing apparatus

Processing instructions selected from a first instruction set in a first processing mode and instructions selected from a second different instruction set in a second processing mode

Element by vector operations in a data processing apparatus

Vector data transfer instruction

Propagation instruction to generate a set of predicate flags based on previous and current prediction data

Vector length querying instruction

Vector atomic memory update instruction

Handling contingent and non-contingent memory access program instructions making use of disable flag

Vector load instruction

Vector operand bitsize control

Vector processing using loops of dynamic vector length

Bit processing

STEPHENS NIGEL JOHN

Address generation in a data processing apparatus

Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands

SEAL DAVID JAMES

Apparatus and method for processing a bitfield manipulation instruction having a control value indicating insertion or extraction form

CRASKE SIMON JOHN

Conditional selection of data elements