Inventor
MANEPALLI RAHUL N
US66 patents
⚠️ This page may combine multiple inventors who share the name “MANEPALLI RAHUL N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
44 patentsUS7948090B2May 24, 2011
Capillary-flow underfill compositions, packages containing same, and systems containing same
INTEL CORP29 citations93
US7033911B2Apr 25, 2006
Adhesive of folded package
INTEL CORP29 citations87
US11164818B2Nov 2, 2021
Inorganic-based embedded-die layers for modular semiconductive devices
INTEL CORP7 citations84
US10170428B2Jan 1, 2019
Cavity generation for embedded interconnect bridges utilizing temporary structures
INTEL CORP7 citations84
US7535114B2May 19, 2009
Integrated circuit devices including compliant material under bond pads and methods of fabrication
INTEL CORP14 citations84
US7151014B2Dec 19, 2006
Underfilling process in a molded matrix array package using flow front modifying solder resist
INTEL CORP12 citations83
US11158558B2Oct 26, 2021
Package with underfill containment barrier
INTEL CORP5 citations82
US11107781B2Aug 31, 2021
RFIC having coaxial interconnect and molded layer
INTEL CORP3 citations73
US10080290B2Sep 18, 2018
Stretchable embedded electronic package
INTEL CORP2 citations73
US9716084B2Jul 25, 2017
Multichip integration with through silicon via (TSV) die embedded in package
INTEL CORP3 citations73
US7339276B2Mar 4, 2008
Underfilling process in a molded matrix array package using flow front modifying solder resist
INTEL CORP5 citations73
US9312233B2Apr 12, 2016
Method of forming molded panel embedded die structure
INTEL CORP5 citations72
US11901248B2Feb 13, 2024
Embedded die architecture and method of making
INTEL CORP2 citations71
US11664290B2May 30, 2023
Package with underfill containment barrier
INTEL CORP3 citations71
US11177232B2Nov 16, 2021
Circuit device with monolayer bonding between surface structures
INTEL CORP2 citations69
US10847471B2Nov 24, 2020
Dielectric filler material in conductive material that functions as fiducial for an electronic device
INTEL CORP2 citations68
US10658281B2May 19, 2020
Integrated circuit substrate and method of making
INTEL CORP2 citations68
US12218040B2Feb 4, 2025
Nested interposer with through-silicon via bridge die
INTEL CORP0 citations63
US12148704B2Nov 19, 2024
Electrical interconnect bridge
INTEL CORP0 citations63
US11791269B2Oct 17, 2023
Electrical interconnect bridge
INTEL CORP1 citations63
US10477688B2Nov 12, 2019
Stretchable electronic assembly
INTEL CORP1 citations63
US12476214B2Nov 18, 2025
Solder interconnect hierarchy for heterogeneous electronic device packaging
INTEL CORP0 citations62
US12300620B2May 13, 2025
Inorganic-based embedded-die layers for modular semiconductive devices
INTEL CORP0 citations62
US11862619B2Jan 2, 2024
Patch accommodating embedded dies having different thicknesses
INTEL CORP1 citations62
US11798887B2Oct 24, 2023
Inorganic-based embedded-die layers for modular semiconductive devices
INTEL CORP0 citations62
US11257748B2Feb 22, 2022
Semiconductor package having polymeric interlayer disposed between conductive elements and dielectric layer
INTEL CORP0 citations62
US9397079B2Jul 19, 2016
Multichip integration with through silicon via (TSV) die embedded in package
INTEL CORP1 citations62
US8009442B2Aug 30, 2011
Directing the flow of underfill materials using magnetic particles
INTEL CORP6 citations62
US12568817B2Mar 3, 2026
Surface functionalization of sinx thin film by wet etching for improved adhesion of metal-dielectric for HSIO
INTEL CORP0 citations61
US12327773B2Jun 10, 2025
Package with underfill containment barrier
INTEL CORP0 citations61
US12068172B2Aug 20, 2024
Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages
INTEL CORP0 citations61
US11955448B2Apr 9, 2024
Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches
INTEL CORP0 citations61
US11935805B2Mar 19, 2024
Package with underfill containment barrier
INTEL CORP0 citations61
US11600563B2Mar 7, 2023
Molded embedded bridge including routing layers for enhanced EMIB applications
INTEL CORP0 citations61
US11276634B2Mar 15, 2022
High density package substrate formed with dielectric bi-layer
INTEL CORP0 citations61
US11081448B2Aug 3, 2021
Embedded die microelectronic device with molded component
INTEL CORP1 citations61
US7816487B2Oct 19, 2010
Die-attach films for chip-scale packaging, packages made therewith, and methods of assembling same
INTEL CORP4 citations61
US12087700B2Sep 10, 2024
Embedded die microelectronic device with molded component
INTEL CORP0 citations60
US11062933B2Jul 13, 2021
Die placement and coupling apparatus
INTEL CORP0 citations60
US11810859B2Nov 7, 2023
Multi-layered adhesion promotion films
INTEL CORP0 citations58
US11527484B2Dec 13, 2022
Dielectric filler material in conductive material that functions as fiducial for an electronic device
INTEL CORP0 citations58
US11508676B2Nov 22, 2022
Density-graded adhesion layer for conductors
INTEL CORP0 citations58
US11291122B2Mar 29, 2022
Apparatus with a substrate provided with plasma treatment
INTEL CORP0 citations58
US7335973B2Feb 26, 2008
Adhesive of folder package
INTEL CORP2 citations57
MANEPALLI RAHUL N
2 patentsRAORANE DIGVIJAY A
1 patentPIETAMBARAM SRINIVAS V
1 patentXU DINGYING
1 patentSTART PAUL R
1 patentShowing the top 50 of 66 patents by PatentIndex Score.