Inventor

THEKKATH RADHIKA

US43 patents

⚠️ This page may combine multiple inventors who share the name “THEKKATH RADHIKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THEKKATH RADHIKA

MIPS TECH INC

Trace control from hardware and software

Trace control based on a characteristic of a processor&#39;s operating state

Coherent data apparatus for an on-chip split transaction system bus

Locked read/write on separate address/data bus using write barrier

Burst-configurable data bus

Processor having a compare extension of an instruction set architecture

Trace control block implementation and method

Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions

Scalable on-chip system bus

Dynamic selection of a compression algorithm for trace data

Optimized external trace formats

External trace synchronization via periodic sampling

Dynamic selection of a compression algorithm for trace data

User controlled trace records

Data release to reduce latency in on-chip system bus

Configurable co-processor interface

Configurable co-processor interface

Program counter and data tracing from a multi-issue processor

Processor having a conditional branch extension of an instruction set architecture

Processor having an arithmetic extension of an instruction set architecture

Tracing out-of order load data

Distributed tap controller

Processor having a compare extension of an instruction set architecture

Configurable co-processor interface

Configurable out-of-order data transfer in a coprocessor interface

System and method for speeding up EJTAG block data transfers

Microprocessor instructions for efficient bit stream extractions

System and method to trace high performance multi-issue processors

Trace control from hardware and software

Trace control from hardware and software

Virtual processor based security for on-chip memory, and applications thereof

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

Configurable co-processor interface

Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion

Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses

Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses

HITACHI LTD

Data streamer

Data cache system

Data streamer

THEKKATH RADHIKA

External trace synchronization via periodic sampling

Systems and methods for controlling the use of processing algorithms, and applications thereof

EQUATOR TECHNOLOGIES INC

Data transfer engine of a processor having a plurality of modules

BERG THOMAS BENJAMIN

Apparatus and method for condensing trace information in a multi-processor system

Trace control based on a characteristic of a processor's operating state