Inventor
KISHORE KARAGADA RAMARAO
US23 patents
⚠️ This page may combine multiple inventors who share the name “KISHORE KARAGADA RAMARAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PAVILION DATA SYSTEMS INC
8 patentsUS10452279B1Oct 22, 2019
Architecture for flash storage server
PAVILION DATA SYSTEMS INC19 citations94
US10467163B1Nov 5, 2019
Solid state drive multiplexer
PAVILION DATA SYSTEMS INC36 citations93
US10289507B1May 14, 2019
Distributed rebuild of failed storage device
PAVILION DATA SYSTEMS INC22 citations93
US10175891B1Jan 8, 2019
Minimizing read latency for solid state drives
PAVILION DATA SYSTEMS INC28 citations93
US10645164B1May 5, 2020
Consistent latency for solid state drives
PAVILION DATA SYSTEMS INC19 citations84
US10509592B1Dec 17, 2019
Parallel data transfer for solid state drives using queue pair subsets
PAVILION DATA SYSTEMS INC8 citations84
US10241722B1Mar 26, 2019
Proactive scheduling of background operations for solid state drives
PAVILION DATA SYSTEMS INC15 citations84
US10216423B1Feb 26, 2019
Streams across multiple controllers to improve solid state drive performance
PAVILION DATA SYSTEMS INC18 citations84
BROADCOM CORP
6 patentsUS7606161B2Oct 20, 2009
Distributing information across equal-cost paths in a network
BROADCOM CORP10 citations84
US9317310B2Apr 19, 2016
Systems and methods for handling virtual machine packets
BROADCOM CORP4 citations73
US7716364B2May 11, 2010
Internet protocol multicast replication
BROADCOM CORP2 citations62
US7284076B2Oct 16, 2007
Dynamically shared memory
BROADCOM CORP2 citations62
US9253121B2Feb 2, 2016
Universal network interface controller
BROADCOM CORP1 citations51
US9515963B2Dec 6, 2016
Universal network interface controller
BROADCOM CORP0 citations47
MIPS TECH INC
3 patentsUS7711934B2May 4, 2010
Processor core and method for managing branch misprediction in an out-of-order processor pipeline
MIPS TECH INC11 citations83
US7721075B2May 18, 2010
Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
MIPS TECH INC3 citations62
US7734901B2Jun 8, 2010
Processor core and method for managing program counter redirection in an out-of-order processor pipeline
MIPS TECH INC2 citations61
AVAGO TECHNOLOGIES GENERAL IP
2 patentsKISHORE KARAGADA RAMARAO
2 patentsUS8145882B1Mar 27, 2012
Apparatus and method for processing template based user defined instructions
KISHORE KARAGADA RAMARAO54 citations92
US8078846B2Dec 13, 2011
Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
KISHORE KARAGADA RAMARAO6 citations59