Inventor

RAJAGOPALAN VIDYA

US12 patents

⚠️ This page may combine multiple inventors who share the name “RAJAGOPALAN VIDYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIPS TECH INC

7 patents

US6493776B1Dec 10, 2002

Processor core and method for managing branch misprediction in an out-of-order processor pipeline

MIPS TECH INC11 citations83

US7159101B1Jan 2, 2007

System and method to trace high performance multi-issue processors

MIPS TECH INC17 citations80

US7721075B2May 18, 2010

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

MIPS TECH INC3 citations62

DIGITAL EQUIPMENT CORP

2 patents

US5341319AAug 23, 1994

Method and apparatus for controlling a rounding operation in a floating point multiplier circuit

DIGITAL EQUIPMENT CORP25 citations91

US5155382AOct 13, 1992

Two-stage CMOS latch with single-wire clock

DIGITAL EQUIPMENT CORP18 citations72

YU MENG-BING

1 patent

US9092343B2Jul 28, 2015

Data cache virtual hint way prediction, and applications thereof

YU MENG-BING19 citations89

KISHORE KARAGADA RAMARAO

1 patent

US8078846B2Dec 13, 2011

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

KISHORE KARAGADA RAMARAO6 citations59

RIVIAN IP HOLDINGS LLC

1 patent

US12374127B2Jul 29, 2025

Heterogeneous on-vehicle camera system for object detection

RIVIAN IP HOLDINGS LLC1 citations58

RAJAGOPALAN VIDYA

MIPS TECH INC

Scalable on-chip system bus

Program counter and data tracing from a multi-issue processor

Data cache virtual hint way prediction, and applications thereof

Low latency system bus interface for multi-master processing environments

Processor core and method for managing branch misprediction in an out-of-order processor pipeline

System and method to trace high performance multi-issue processors

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

DIGITAL EQUIPMENT CORP

Method and apparatus for controlling a rounding operation in a floating point multiplier circuit

Two-stage CMOS latch with single-wire clock

YU MENG-BING

Data cache virtual hint way prediction, and applications thereof

KISHORE KARAGADA RAMARAO

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

RIVIAN IP HOLDINGS LLC

Heterogeneous on-vehicle camera system for object detection