Inventor

LATORRE FERNANDO

ES35 patents

⚠️ This page may combine multiple inventors who share the name “LATORRE FERNANDO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LATORRE FERNANDO

INTEL CORP

Multithreaded clustered microarchitecture with dynamic back-end assignment

Reconfigurable processing unit

Processing device for performing convolution operations

Storage device and method for performing convolution operations

Cache sharing based thread control

Adaptive data prefetching

Register allocation technique

Instruction and logic for support of code modification in translation lookaside buffers

Processing device for performing convolution operations

Two-level cache locking mechanism

Multithreaded clustered microarchitecture with dynamic back-end assignment

Method and apparatus for distributed and cooperative computation in artificial neural networks

Reconfigurable processing unit

Method and apparatus for distributed and cooperative computation in artificial neural networks

Merging level cache and data cache units having indicator bits related to speculative execution

Method and apparatus to implement lazy flush in a virtually tagged cache memory

Instruction and logic for support of code modification in translation lookaside buffers

Processing device for performing convolution operations

Instruction and logic for bulk register reclamation

Instruction and logic for optimization level aware branch prediction

Cache coherency and processor consistency

Store forwarding for data caches

LATORRE FERNANDO

Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution

Multithreaded clustered microarchitecture with dynamic back-end assignment

Achieving coherence between dynamically optimized code and original code

LOPEZ PEDRO

Replacement policy for hot code detection

Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

CONECTATE SOLUCIONES Y APLICACIONES SL

Unified identification protocol in training and health

Method of a universal registration and identification of legal procedures

GIMENO CARLOS MADRILES

Enabling speculative state information in a cache coherency protocol

GIBERT ENRIC

Access of register files of other threads using synchronization

TOPP JAROSLAW

Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset

VALLOUREC TUBOS DO BRASIL S A

Process and reactor for continuous charcoal production

STAVROU KYRIAKOS A

Managed instruction cache prefetching

MARTINEZ RAUL

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region