Inventor

KISSELL KEVIN D

FR46 patents

⚠️ This page may combine multiple inventors who share the name “KISSELL KEVIN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KISSELL KEVIN D

MIPS TECH INC

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Mechanisms for dynamic configuration of virtual processor resources

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

Mechanisms for assuring quality of service for programs executing on a multithreaded processor

Virtual machine coprocessor facilitating dynamic compilation

System, method, and computer program product for conditionally suspending issuing instructions of a thread

Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Method and apparatus for disassociating power consumed within a processing system with instructions it is executing

System for prediction and control of power consumption in digital system

Software emulation of directed exceptions in a multithreading processor

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration

Mechanism for proxy management of multiprocessor virtual memory

Mechanism for proxy management of multiprocessor storage hierarchies

Mechanism for programmable modification of memory mapping granularity

Mechanism for extending properties of virtual memory pages by a TLB

Partial bitwise permutations

Instruction specified register value saving in allocated caller stack or not yet allocated callee stack

Mechanism to extend computer memory protection schemes

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Synchronized storage providing multiple synchronization semantics

Microprocessor instructions for performing polynomial arithmetic operations

Method and apparatus for masking a microprocessor execution signature

Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler

Smart memory based synchronization controller for a multi-threaded multiprocessor SoC

Programmable page table access

Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack

KISSELL KEVIN D

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Virtual machine coprocessor for accelerating software execution

Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor

Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Substituting portion of template instruction parameter with selected virtual instruction parameter

ARM FINANCE OVERSEAS LTD

Virtual machine coprocessor for accelerating software execution

Virtual machine coprocessor for accelerating software execution

System and method for improving memory transfer

GOOGLE INC

Authenticating shared interconnect fabrics

SEREBRIN BENJAMIN CHARLES

Emulating eviction data paths for invalidated instruction cache

KISHORE KARAGADA R

System and method for improving memory transfer