Inventor
KHANDEKAR NARENDRA S
US14 patents
Patents
14 patentsUS6981089B2Dec 27, 2005
Memory bus termination with memory unit having termination control
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Memory buffer arrangement
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US7353329B2Apr 1, 2008
Memory buffer device integrating refresh logic
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US6832177B2Dec 14, 2004
Method of addressing individual memory devices on a memory module
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US6243768B1Jun 5, 2001
Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
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US5926828AJul 20, 1999
Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
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US6157397ADec 5, 2000
AGP read and CPU wire coherency
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US6502150B1Dec 31, 2002
Method and apparatus for resource sharing in a multi-processor system
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US5873119AFeb 16, 1999
Method for parallel processing of dram read request in a memory-cache controller system
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US6976121B2Dec 13, 2005
Apparatus and method to track command signal occurrence for DRAM data transfer
INTEL CORP5 citations62
US6829184B2Dec 7, 2004
Apparatus and method for encoding auto-precharge
INTEL CORP5 citations62
US6385703B1May 7, 2002
Speculative request pointer advance for fast back-to-back reads
INTEL CORP5 citations62
US6314497B1Nov 6, 2001
Apparatus and method for maintaining cache coherency in a memory system
INTEL CORP2 citations61
US6976120B2Dec 13, 2005
Apparatus and method to track flag transitions for DRAM data transfer
INTEL CORP0 citations52