Inventor

ACHUTHAN KRISHNASHREE

US33 patents

⚠️ This page may combine multiple inventors who share the name “ACHUTHAN KRISHNASHREE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ACHUTHAN KRISHNASHREE

ADVANCED MICRO DEVICES INC

Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed

Multi-step chemical mechanical polishing of a gate area in a FinFET

Dual silicon layer for chemical mechanical polishing planarization

Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure

Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect

Method for effectively removing polysilicon nodule defects

Methods for reduced trench isolation step height

Tightly spaced gate formation through damascene process

Hard mask removal process including isolation dielectric refill

Multi-step chemical mechanical polishing of a gate area in a FinFET

Flash memory cell with UV protective layer

Dual silicon layer for chemical mechanical polishing planarization

Dual silicon layer for chemical mechanical polishing planarization

Method of manufacturing a seed layer with annealed region for integrated circuit interconnects

Methods for trench isolation with reduced step height

Seed layer with annealed region for integrated circuit interconnects

Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure

Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby

Dielectric protected chemical-mechanical polishing in integrated circuit interconnects

Self-aligned polysilicon polish

Method for reducing edge array erosion in a high-density array

Method for semiconductor wafer planarization by isolation material growth

Method for semiconductor wafer planarization by CMP stop layer formation

Method for minimizing nitride residue on a silicon wafer

Semiconductor wafer polishing apparatus

Differential pressure chemical-mechanical polishing in integrated circuit interconnects

SPANSION LLC

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

Method for decreasing sheet resistivity variations of an interconnect metal layer

Method for controlling poly 1 thickness and uniformity in a memory array fabrication process

AMRITA VISHWA VIDYAPEETHAM

Intelligent “IoT gateway”

Security layer and methods for protecting tenant data in a cloud-mediated computing network

SATHYADEVAN SHIJU

Security layer and methods for protecting tenant data in a cloud-mediated computing network

FREEMAN JOSHUA DAVID

Solar monitoring system for measuring solar radiation intensity