Inventor

BANNON PETER J

US24 patents

⚠️ This page may combine multiple inventors who share the name “BANNON PETER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BANNON PETER J

DIGITAL EQUIPMENT CORP

High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy

Cache memory system

Method for increasing system bandwidth through an on-chip address lock register

System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command

Cache with at least two fill rates

System interface protocol with optional module cache

Autonomous pipeline reconfiguration for continuous error correction for fills from tertiary cache or memory

HEWLETT PACKARD DEVELOPMENT CO

Fault containment and error recovery in a scalable multiprocessor

Fault containment and error recovery in a scalable multiprocessor

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

Mechanism to track all open pages in a DRAM memory system

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

APPLE INC

Combining write buffer with dynamically adjustable flush metrics

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

Data cache block zero implementation

Combining write buffer with dynamically adjustable flush metrics

GUNNA RAMESH B

Maintaining the integrity of an execution return address stack

Lookahead scanning and cracking of microcode instructions in a dispatch queue

COMPAQ INFORMATION TECHNOLOGIE

Proprammable DRAM address mapping mechanism

COMPAQ COMPUTER CORP

Apparatus and method for operating clock sensitive devices in multiple timing domains

MURRAY DANIEL C

Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle

GUNNA RAMESH

Data cache block zero implementation

BEAUMONT-SMITH ANDREW J

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

BANNON PETER J

Fused store exclusive/memory barrier operation