Inventor
MCDONNELL NIALL D
IE23 patents
Patents
23 patentsUS11693691B2Jul 4, 2023
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations85
US12026116B2Jul 2, 2024
Network and edge acceleration tile (NEXT) architecture
INTEL CORP8 citations83
US11416281B2Aug 16, 2022
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP4 citations83
US11093277B2Aug 17, 2021
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP6 citations83
US10966135B2Mar 30, 2021
Software-defined networking data re-direction
INTEL CORP7 citations82
US10445271B2Oct 15, 2019
Multi-core communication acceleration using hardware queue device
INTEL CORP7 citations82
US12135981B2Nov 5, 2024
Systems, methods, and apparatuses for heterogeneous computing
INTEL CORP1 citations72
US10572260B2Feb 25, 2020
Spatial and temporal merging of remote atomic operations
INTEL CORP2 citations72
US9553853B2Jan 24, 2017
Techniques for load balancing in a packet distribution system
INTEL CORP3 citations72
US11641608B2May 2, 2023
Software-defined networking data re-direction
INTEL CORP2 citations71
US11500636B2Nov 15, 2022
Spatial and temporal merging of remote atomic operations
INTEL CORP0 citations62
US10884970B2Jan 5, 2021
Techniques for coalescing doorbells in a request message
INTEL CORP0 citations62
US11080202B2Aug 3, 2021
Lazy increment for high frequency counters
INTEL CORP0 citations61
US10929323B2Feb 23, 2021
Multi-core communication acceleration using hardware queue device
INTEL CORP1 citations61
US6981113B2Dec 27, 2005
Storage registers for a processor pipeline
INTEL CORP5 citations61
US8024594B2Sep 20, 2011
Method and apparatus for reducing power consumption in multi-channel memory controller systems
INTEL CORP4 citations60
US11489791B2Nov 1, 2022
Virtual switch scaling for networking applications
INTEL CORP0 citations56
US11134021B2Sep 28, 2021
Techniques for processor queue management
INTEL CORP0 citations51
US7450576B2Nov 11, 2008
Timeslot assignment
INTEL CORP0 citations51
US7243214B2Jul 10, 2007
Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary
INTEL CORP0 citations51
US7317737B2Jan 8, 2008
Systems and methods for using HDLC channel context to simultaneously process multiple HDLC channels
INTEL CORP0 citations45
US10635590B2Apr 28, 2020
Software-transparent hardware predictor for core-to-core data transfer optimization
INTEL CORP0 citations41
US10606751B2Mar 31, 2020
Techniques for cache delivery
INTEL CORP0 citations41