Inventor
FENG KAI DI
US34 patents
⚠️ This page may combine multiple inventors who share the name “FENG KAI DI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
28 patentsUS6175434B1Jan 16, 2001
Adaptive infrared communication apparatus
IBM119 citations98
US7061359B2Jun 13, 2006
On-chip inductor with magnetic core
IBM27 citations93
US6111441AAug 29, 2000
Zero power power-on reset bootstrapping method and apparatus for ultra low-power integrated circuit packaging
IBM21 citations93
US7012440B2Mar 14, 2006
Wafer test apparatus including optical elements and method of using the test apparatus
IBM25 citations92
US6990644B2Jan 24, 2006
On chip timing adjustment in multi-channel fast data transfer
IBM15 citations92
US6731122B2May 4, 2004
Wafer test apparatus including optical elements and method of using the test apparatus
IBM36 citations92
US9189654B2Nov 17, 2015
On-chip structure for security application
IBM9 citations84
US7930664B2Apr 19, 2011
Programmable through silicon via
IBM7 citations84
US7839163B2Nov 23, 2010
Programmable through silicon via
IBM12 citations84
US7538622B2May 26, 2009
Multiple reference frequency fractional-N PLL (phase locked loop)
IBM11 citations84
US7271693B2Sep 18, 2007
On-chip inductor with magnetic core
IBM13 citations84
US7816945B2Oct 19, 2010
3D chip-stack with fuse-type through silicon via
IBM7 citations74
US6700424B2Mar 2, 2004
Multiple-channel optical transceiver input buffer with zero static current and symmetrical hysteresis
IBM11 citations74
US9252794B1Feb 2, 2016
Frequency calibration with real-time resistor trimming
IBM4 citations73
US7471160B2Dec 30, 2008
Real-time frequency band selection circuit for use with a voltage controlled oscillator
IBM8 citations73
US7926015B2Apr 12, 2011
Optimization method for fractional-N phased-lock-loop (PLL) system
IBM2 citations63
US7750697B2Jul 6, 2010
Fractional-N phased-lock-loop (PLL) system
IBM3 citations63
US7627835B2Dec 1, 2009
Frequency divider monitor of phase lock loop
IBM3 citations63
US7487481B2Feb 3, 2009
Receiver circuit for on chip timing adjustment
IBM4 citations63
US7472362B1Dec 30, 2008
Method of minimizing phase noise
IBM2 citations63
US7362184B2Apr 22, 2008
Frequency divider monitor of phase lock loop
IBM4 citations63
US7250778B2Jul 31, 2007
Wafer test apparatus including optical elements and method of using the test apparatus
IBM2 citations63
US6034802AMar 7, 2000
Wireless communications systems with self threshold setting
IBM4 citations63
US7759789B2Jul 20, 2010
Local area semiconductor cooling system
IBM2 citations62
US7961032B1Jun 14, 2011
Method of and structure for recovering gain in a bipolar transistor
IBM1 citations52
US7962322B2Jun 14, 2011
Design structure for compensating for variances of a buried resistor in an integrated circuit
IBM1 citations50
US7402890B2Jul 22, 2008
Method for symmetric capacitor formation
IBM0 citations42
US7886237B2Feb 8, 2011
Method of generating a functional design structure
IBM0 citations40
FENG KAI DI
3 patentsUS8211756B2Jul 3, 2012
3D chip-stack with fuse-type through silicon via
FENG KAI DI15 citations83
US8122395B2Feb 21, 2012
On chip timing adjustment in multi-channel fast data transfer
FENG KAI DI5 citations72
US8086974B2Dec 27, 2011
Structure for fractional-N phased-lock-loop (PLL) system
FENG KAI DI2 citations61