Inventor
CHEN CHIA-LIN
TW35 patents
⚠️ This page may combine multiple inventors who share the name “CHEN CHIA-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
24 patentsUS7259050B2Aug 21, 2007
Semiconductor device and method of making the same
TAIWAN SEMICONDUCTOR MFG75 citations98
US7052946B2May 30, 2006
Method for selectively stressing MOSFETs to improve charge carrier mobility
TAIWAN SEMICONDUCTOR MFG84 citations98
US7268575B1Sep 11, 2007
Method of NBTI prediction
TAIWAN SEMICONDUCTOR MFG41 citations94
US7176138B2Feb 13, 2007
Selective nitride liner formation for shallow trench isolation
TAIWAN SEMICONDUCTOR MFG15 citations92
US7118974B2Oct 10, 2006
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG22 citations92
US7071066B2Jul 4, 2006
Method and structure for forming high-k gates
TAIWAN SEMICONDUCTOR MFG46 citations92
US6759302B1Jul 6, 2004
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG35 citations92
US6737362B1May 18, 2004
Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication
TAIWAN SEMICONDUCTOR MFG20 citations92
US6821868B2Nov 23, 2004
Method of forming nitrogen enriched gate dielectric with low effective oxide thickness
TAIWAN SEMICONDUCTOR MFG33 citations88
US7579859B2Aug 25, 2009
Method for determining time dependent dielectric breakdown
TAIWAN SEMICONDUCTOR MFG11 citations84
US7820457B2Oct 26, 2010
Method of NBTI prediction
TAIWAN SEMICONDUCTOR MFG10 citations82
US7696578B2Apr 13, 2010
Selective CESL structure for CMOS application
TAIWAN SEMICONDUCTOR MFG10 citations78
US7138317B2Nov 21, 2006
Method of generating multiple oxides by plasma nitridation on oxide
TAIWAN SEMICONDUCTOR MFG9 citations74
US6861339B2Mar 1, 2005
Method for fabricating laminated silicon gate electrode
TAIWAN SEMICONDUCTOR MFG7 citations74
US6780741B2Aug 24, 2004
Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers
TAIWAN SEMICONDUCTOR MFG9 citations74
US7327009B2Feb 5, 2008
Selective nitride liner formation for shallow trench isolation
TAIWAN SEMICONDUCTOR MFG5 citations73
US6933157B2Aug 23, 2005
Semiconductor wafer manufacturing methods employing cleaning delay period
TAIWAN SEMICONDUCTOR MFG2 citations63
US6830996B2Dec 14, 2004
Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
TAIWAN SEMICONDUCTOR MFG3 citations63
US7361572B2Apr 22, 2008
STI liner modification method
TAIWAN SEMICONDUCTOR MFG4 citations62
US7012009B2Mar 14, 2006
Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process
TAIWAN SEMICONDUCTOR MFG6 citations62
US7316970B2Jan 8, 2008
Method for forming high selectivity protection layer on semiconductor device
TAIWAN SEMICONDUCTOR MFG0 citations52
US7229919B2Jun 12, 2007
Semiconductor device having a random grained polysilicon layer and a method for its manufacture
TAIWAN SEMICONDUCTOR MFG0 citations52
US7166525B2Jan 23, 2007
High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer
TAIWAN SEMICONDUCTOR MFG1 citations52
US7453280B1Nov 18, 2008
Method for testing semiconductor devices
TAIWAN SEMICONDUCTOR MFG1 citations49
CHEN CHIA-LIN
3 patentsUS8106461B2Jan 31, 2012
Apparatus for NBTI prediction
CHEN CHIA-LIN6 citations81
US8115263B2Feb 14, 2012
Laminated silicon gate electrode
CHEN CHIA-LIN0 citations51
US9406825B2Aug 2, 2016
Stacked and integrated electric power generating device capturing multiple light sources for power generation
CHEN CHIA-LIN0 citations41