Inventor

MCDEVITT THOMAS L

US51 patents

⚠️ This page may combine multiple inventors who share the name “MCDEVITT THOMAS L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCDEVITT THOMAS L

IBM

Interconnection structure and method for fabricating same

Fluorine-free barrier layer between conductor and insulator for degradation prevention

Fluorine barrier layer between conductor and insulator for degradation prevention

Method for providing fluorine barrier layer between conductor and insulator for degradation prevention

Fluorine barrier layer between conductor and insulator for degradation prevention

Crack stop for low K dielectrics

Exposed pore sealing post patterning

Electrical detection of dicing damage

Triple damascene fuse

Tri-layer dielectric fuse cap for laser deletion

Method for applying photoresist

Crack stop for low K dielectrics

Method of fabricating copper damascene and dual damascene interconnect wiring

Two step annealing process for decreasing contact resistance

Vertical integrated circuit switches, design structure and methods of fabricating same

Dual damascene wiring and method

Exposed pore sealing post patterning

Insulative cap for laser fusing

Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed

Interconnection structure and method for fabricating same

Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed

Local plasma processing

Dual damascene wiring and method

Bilayer aluminum last metal for interconnects and wirebond pads

Method for fabricating a triple damascene fuse

Insulative cap for laser fusing

Metal seed layer deposition

Method of fabricating copper damascene and dual damascene interconnect wiring

Metal seed layer deposition

Copper to aluminum interlayer interconnect using stud and via liner

Copper to aluminum interlayer interconnect using stud and via liner

Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing

Horizontal coplanar switches and methods of manufacture

Integrated circuit switches, design structure and methods of fabricating the same

System and method for forming an aluminum fuse for compatibility with copper BEOL interconnect scheme

Method of fabricating copper damascene and dual damascene interconnect wiring

Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing

ANDERSON FELIX P

Vertical integrated circuit switches, design structure and methods of fabricating same

Integrated circuit switches, design structure and methods of fabricating the same

System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme

Horizontal coplanar switches and methods of manufacture

Structures and methods for improving solder bump connections in semiconductor devices

Methods of manufacturing semiconductor devices and a semiconductor structure

COONEY III EDWARD C

Structure and method for reducing vertical crack propagation

(unassigned)

Method of depositing conductors in high aspect ratio apertures using a collimator

CHRISMAN GREGORY S

Top corner rounding of damascene wire for insulator crack suppression

GAMBINO JEFFREY P

Copper damascene and dual damascene interconnect wiring

LEE TOM C

Electrical fuse with a current shunt

MCDEVITT THOMAS L

CMP method

AMOAH YOBA

Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics