Inventor
AZIZ PERVEZ M
US44 patents
⚠️ This page may combine multiple inventors who share the name “AZIZ PERVEZ M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AGERE SYSTEMS INC
21 patentsUS7411531B2Aug 12, 2008
Methods and apparatus for asynchronous sampling of a received signal at a downsampled rate
AGERE SYSTEMS INC69 citations98
US7180693B2Feb 20, 2007
Method and apparatus for maximum likelihood detection of data employing interpolation with compensation of signal asymmetry
AGERE SYSTEMS INC71 citations98
US7167328B2Jan 23, 2007
Synchronizing an asynchronously detected servo signal to synchronous servo demodulation
AGERE SYSTEMS INC79 citations98
US7092462B2Aug 15, 2006
Asynchronous servo RRO detection employing interpolation
AGERE SYSTEMS INC80 citations98
US7002767B2Feb 21, 2006
Detection of recorded data employing interpolation with gain compensation
AGERE SYSTEMS INC80 citations98
US6912099B2Jun 28, 2005
Maximum likelihood detection of asynchronous servo data employing interpolation
AGERE SYSTEMS INC83 citations98
US6751774B2Jun 15, 2004
Rate (M/N) code encoder, detector, and decoder for control data
AGERE SYSTEMS INC20 citations92
US6606728B1Aug 12, 2003
Rate (M/N) code encoder, detector, and decoder for control data
AGERE SYSTEMS INC16 citations92
US6480984B1Nov 12, 2002
Rate (M/N) code encoder, detector, and decoder for control data
AGERE SYSTEMS INC25 citations92
US8027409B2Sep 27, 2011
Noise prediction-based signal detection and cross-talk mitigation
AGERE SYSTEMS INC18 citations84
US7916822B2Mar 29, 2011
Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit
AGERE SYSTEMS INC7 citations84
US7616686B2Nov 10, 2009
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data
AGERE SYSTEMS INC17 citations84
US7599461B2Oct 6, 2009
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern
AGERE SYSTEMS INC13 citations84
US7231001B2Jun 12, 2007
Processing servo data having DC level shifts
AGERE SYSTEMS INC12 citations84
US7466766B2Dec 16, 2008
Processing servo data having DC level shifts
AGERE SYSTEMS INC5 citations74
US8054892B2Nov 8, 2011
Compensating transmission line to reduce sensitivity of performance due to channel length variation
AGERE SYSTEMS INC5 citations70
US7756235B2Jul 13, 2010
Methods and apparatus for digital compensation of clock errors for a clock and data recovery circuit
AGERE SYSTEMS INC3 citations63
US7606301B2Oct 20, 2009
Method and apparatus for adaptively establishing a sampling phase for decision-feedback equalization
AGERE SYSTEMS INC6 citations63
US7583458B2Sep 1, 2009
Channel optimization metrics
AGERE SYSTEMS INC5 citations63
US7502427B2Mar 10, 2009
Asynchronous servo RRO detection employing interpolation
AGERE SYSTEMS INC4 citations63
US7792234B2Sep 7, 2010
Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system
AGERE SYSTEMS INC1 citations52
AZIZ PERVEZ M
9 patentsUS8107522B2Jan 31, 2012
Methods and apparatus for determining receiver filter coefficients for a plurality of phases
AZIZ PERVEZ M8 citations84
US8467440B2Jun 18, 2013
Compensated phase detector for generating one or more clock signals using DFE detected data in a receiver
AZIZ PERVEZ M7 citations82
US8743945B2Jun 3, 2014
Shift register based downsampled floating tap decision feedback equalization
AZIZ PERVEZ M5 citations70
US8279950B2Oct 2, 2012
Compensation for transmission line length variation in a SERDES system
AZIZ PERVEZ M5 citations70
US8902963B2Dec 2, 2014
Methods and apparatus for determining threshold of one or more DFE transition latches based on incoming data eye
AZIZ PERVEZ M3 citations62
US8761237B2Jun 24, 2014
Low nonlinear distortion variable gain amplifier
AZIZ PERVEZ M2 citations62
US8432959B2Apr 30, 2013
Method and apparatus for equalization using one or more qualifiers
AZIZ PERVEZ M3 citations62
US8315298B2Nov 20, 2012
Method and apparatus for rate-dependent equalization
AZIZ PERVEZ M2 citations62
US8416907B2Apr 9, 2013
Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system
AZIZ PERVEZ M1 citations52
LSI CORP
8 patentsUS9106462B1Aug 11, 2015
Reduced power SERDES receiver using selective adaptation of equalizer parameters in response to supply voltage and operating temperature variations and technique for measuring same
LSI CORP49 citations94
US8860467B2Oct 14, 2014
Biased bang-bang phase detector for clock and data recovery
LSI CORP12 citations82
US9294314B2Mar 22, 2016
Receiver having limiter-enhanced data eye openings
LSI CORP3 citations73
US9143367B2Sep 22, 2015
Clock and data recovery architecture with adaptive digital phase skew
LSI CORP4 citations73
US8379711B2Feb 19, 2013
Methods and apparatus for decision-feedback equalization with oversampled phase detector
LSI CORP6 citations72
US8831142B2Sep 9, 2014
Adaptive cancellation of voltage offset in a communication system
LSI CORP6 citations71
US8908816B2Dec 9, 2014
Receiver with distortion compensation circuit
LSI CORP1 citations52
US9397674B2Jul 19, 2016
Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
LSI CORP0 citations49
LUCENT TECHNOLOGIES INC
3 patentsUS6130629AOct 10, 2000
Rate 24/25 (0,9) code method and system for PRML recording channels
LUCENT TECHNOLOGIES INC17 citations91
US6046691AApr 4, 2000
Rate 16/17 (0,5) modulation code apparatus and method for partial response magnetic recording channels
LUCENT TECHNOLOGIES INC28 citations91
US6204781B1Mar 20, 2001
General rate N/(N+1) (0, G) code construction for data coding
LUCENT TECHNOLOGIES INC18 citations80