Inventor

SOHN HAN-GU

KR29 patents

⚠️ This page may combine multiple inventors who share the name “SOHN HAN-GU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOHN HAN-GU

SAMSUNG ELECTRONICS CO LTD

Multiprocessor system and method thereof

Multi-port memory device for buffering between hosts and non-volatile memory devices

Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory

Multi-port memory device for buffering between hosts

Non volatile semiconductor memory device having a multi-bit cell array

System having memory device accessible to multiple processors

Multi-port memory device for buffering between hosts and non-volatile memory devices

Circuits and methods for providing variable data I/O width for semiconductor memory devices

Semiconductor memory device performing partial self refresh and memory system including same

Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level

Arbitration for memory device with commands

Memory system and method ensuring read data stability

Multipath accessible semiconductor memory device with host interface between processors

Multi-port memory device providing protection signal

Semiconductor memory device and method for masking predetermined area of memory cell array during write operation

Non-volatile memory systems and methods of managing power of the same

Memory expansion structure in multi-path accessible semiconductor memory device

Non-volatile memory systems and methods of managing power of the same

Multi-path accessible semiconductor memory device with prevention of pre-charge skip

KWON JIN-HYOUNG

Multi processor system having direct access boot and direct access boot method thereof

Semiconductor memory device having processor reset function and reset control method thereof

Multi port memory device with shared memory area using latch type memory cells and driving method

Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to stored messages in an internal register

SOHN HAN-GU

Method of controlling refresh operation in multi-port DRAM and a memory system using the method

Bootable volatile memory device, memory module and processing system comprising bootable volatile memory device, and method of booting processing system using bootable volatile memory device

IM JEON-TAEK

Memory system and memory management method including the same

KIM DOO-GON

Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same

LEE YOUNG-MIN

Arbitration for memory device with commands

JU JAE-HYEON

Non-volatile memory systems and methods of managing power of the same