Inventor

FEUSTEL FRANK

DE53 patents

⚠️ This page may combine multiple inventors who share the name “FEUSTEL FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEUSTEL FRANK

GLOBALFOUNDRIES INC

Fabricating vias of different size of a semiconductor device by splitting the via patterning process

Test structure for monitoring leakage currents in a metallization layer

Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size

Method for preventing the formation of electrical shorts via contact ILD voids

Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices

Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structure

Restricted stress regions formed in the contact level of a semiconductor device

Method and test structure for estimating focus settings in a lithography process based on CD measurements

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Wafer with improved plating current distribution

Wafer with improved plating current distribution

ADVANCED MICRO DEVICES INC

Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Field effect transistor having a stressed contact etch stop layer with reduced conformality

Test structure for OPC-related shorts between lines in a semiconductor device

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics

Method of forming an etch indicator layer for reducing etch non-uniformities

Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly

Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge

Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor

Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines

FEUSTEL FRANK

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

Metallization system of a semiconductor device comprising extra-tapered transition vias

Method of selectively forming a conductive barrier layer by ALD

Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices

Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer

Reducing copper defects during a wet chemical cleaning of exposed copper surfaces in a metallization layer of a semiconductor device

WERNER THOMAS

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

GRIEBENOW UWE

Method for increasing penetration depth of drain and source implantation species for a given gate height

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Method for increasing penetration depth of drain and source implantation species for a given gate height

SEIDEL ROBERT

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Semiconductor device comprising a carbon-based material for through hole vias

HUISINGA TORSTEN

Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features

Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction

LETZ TOBIAS

Local silicidation of via bottoms in metallization systems of semiconductor devices

Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge

HEINRICH JENS

Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation

FROHBERG KAI

Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach

GLOBALFOUNDDRIES INC

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

RICHTER RALF

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

AUBEL OLIVER

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices