Inventor

IYER MAHESH A

US73 patents

⚠️ This page may combine multiple inventors who share the name “IYER MAHESH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYER MAHESH A

INTEL CORP

Sharing a JTAG interface among multiple partitions

Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks

Methods for delaying register reset for retimed circuits

Fast memory for programmable devices

On-die aging measurements for dynamic timing modeling

Methods and apparatus to insert buffers in a dataflow graph

Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph

Techniques for providing optimizations based on categories of slack in timing paths

Methods for verifying retimed circuits with delayed initialization

Methods for bounding the number of delayed reset clock cycles for retimed circuits

Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop

Switch based on load current

Workload-dependent integrated circuit operation based on power headroom

Dynamic loadlines for programmable fabric devices

Systems and methods to reduce voltage guardband

Fast memory for programmable devices

Methods and apparatus for reducing reliability degradation on an integrated circuit

Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks

SYNOPSYS INC

Interconnect-driven physical synthesis using persistent virtual routing

Adaptive cell separation and circuit changes driven by maximum capacitance rules

Solving an optimization problem using a constraints solver

Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solver

Identifying candidate nets for buffering using numerical methods

Solving a gate-sizing optimization problem using a constraints solver

Incremental slack margin propagation

Robust numerical optimization for optimizing delay, area, and leakage power

Modeling gate size range by using a penalty function in a numerical gate sizing framework

Modeling transition effects for circuit optimization

ALTERA CORP

Method and apparatus for verifying structural correctness in retimed circuits

Integrated circuit retiming with selective modeling of flip-flop secondary signals

Sector-based clock routing methods and apparatus

Partial reconfiguration debugging using hybrid models

Method and apparatus for performing register retiming by utilizing native timing-driven constraints

Methods for incremental circuit design legalization during physical synthesis

Methods for incremental circuit physical synthesis

Method and apparatus for performing clock allocation for a system implemented on a programmable device

Methods for minimizing logic overlap on integrated circuits

IYER MAHESH A

Zone-based leakage power optimization

Excluding library cells for delay optimization in numerical synthesis

Incremental elmore delay calculation

Delta-slack propagation for circuit optimization

MOTTAEZ AMIR H

Hyper-concurrent optimization over multi-corner multi-mode scenarios

Optimizing a circuit design for delay using load-and-slew-independent numerical delay models

Performing scenario reduction using a dominance relation on a set of corners

WALKER ROBERT

Zone-based area recovery in electronic design automation

Zone-based optimization framework for performing timing and design rule optimization

Density-based area recovery in electronic design automation

LUCENT TECHNOLOGIES INC

Method for identifying untestable faults in logic circuits

Method for identifying untestable and redundant faults in sequential logic circuits.

IBM

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