Inventor

MOTTAEZ AMIR H

US26 patents

⚠️ This page may combine multiple inventors who share the name “MOTTAEZ AMIR H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOTTAEZ AMIR H

SYNOPSYS INC

Solving an optimization problem using a constraints solver

Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solver

Identifying candidate nets for buffering using numerical methods

Solving a gate-sizing optimization problem using a constraints solver

Incremental slack margin propagation

Robust numerical optimization for optimizing delay, area, and leakage power

Modeling gate size range by using a penalty function in a numerical gate sizing framework

Modeling transition effects for circuit optimization

Efficient timing calculations in numerical sequential cell sizing and incremental slack margin propagation

Numerical area recovery

Numerical delay model for a technology library cell type

Sequential sizing in physical synthesis

Discretizing gate sizes during numerical synthesis

MOTTAEZ AMIR H

Hyper-concurrent optimization over multi-corner multi-mode scenarios

Optimizing a circuit design for delay using load-and-slew-independent numerical delay models

Performing scenario reduction

Performing scenario reduction using a dominance relation on a set of corners

Performing scenario reduction in a circuit design flow

Estimating optimal gate sizes by using numerical delay models

IYER MAHESH A

Excluding library cells for delay optimization in numerical synthesis

Incremental elmore delay calculation

Numerical delay model for a technology library cell

Method and apparatus for determining a robustness metric for a circuit design

Determining optimal gate sizes by using a numerical solver

Global timing modeling within a local context

WALKER ROBERT

Zone-based optimization framework for performing timing and design rule optimization