Inventor
QUAY STEPHEN T
US16 patents
⚠️ This page may combine multiple inventors who share the name “QUAY STEPHEN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS9092591B2Jul 28, 2015
Automatic generation of wire tag lists for a metal stack
IBM6 citations83
US8769468B1Jul 1, 2014
Automatic generation of wire tag lists for a metal stack
IBM6 citations83
US8365120B2Jan 29, 2013
Resolving global coupling timing and slew violations for buffer-dominated designs
IBM11 citations83
US7484199B2Jan 27, 2009
Buffer insertion to reduce wirelength in VLSI circuits
IBM9 citations83
US8881089B1Nov 4, 2014
Physical synthesis optimization with fast metric check
IBM11 citations82
US7448007B2Nov 4, 2008
Slew constrained minimum cost buffering
IBM9 citations82
US7895557B2Feb 22, 2011
Concurrent buffering and layer assignment in integrated circuit layout
IBM10 citations80
US9875326B2Jan 23, 2018
Addressing coupled noise-based violations with buffering in a batch environment
IBM3 citations72
US9038009B2May 19, 2015
Early design cycle optimization
IBM3 citations61
US7890905B2Feb 15, 2011
Slew constrained minimum cost buffering
IBM4 citations60
US10503841B2Dec 10, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10496764B2Dec 3, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10372836B2Aug 6, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10372837B2Aug 6, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52
US10346558B2Jul 9, 2019
Integrated circuit buffering solutions considering sink delays
IBM0 citations52