Inventor

MALI JIM

US52 patents

⚠️ This page may combine multiple inventors who share the name “MALI JIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MALI JIM

BECKER SCOTT T

Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts

Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature

Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes

Finfet transistor circuit

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel

Circuits with linear finfet structures

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications

Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors

Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors

Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature

Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications

Cross-coupled transistor circuit including offset inner gate contacts

Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer

Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact

TELA INNOVATIONS INC

Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track

Enforcement of semiconductor structure regularity for localized transistors and interconnect

Enforcement of semiconductor structure regularity for localized transistors and interconnect

Integrated circuit within semiconductor chip including cross-coupled transistor configuration

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods

Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods

Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature

Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures

Cross-coupled transistor circuit defined on four gate electrode tracks

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends

Enforcement of semiconductor structure regularity for localized transistors and interconnect

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

KORNACHUK STEPHEN

Enforcement of semiconductor structure regularity for localized transistors and interconnect

ARM PHYSICAL IP INC

Dual port memory core cell architecture with matched bit line capacitances