Inventor
GARG MANISH
US56 patents
⚠️ This page may combine multiple inventors who share the name “GARG MANISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
21 patentsUS9870818B1Jan 16, 2018
Separate read and write address decoding in a memory system to support simultaneous memory read and write operations
QUALCOMM INC10 citations84
US8008961B2Aug 30, 2011
Adaptive clock generators, systems, and methods
QUALCOMM INC13 citations84
US9093125B2Jul 28, 2015
Low voltage write speed bitcell
QUALCOMM INC15 citations78
US8976618B1Mar 10, 2015
Decoded 2N-bit bitcells in memory for storing decoded bits, and related systems and methods
QUALCOMM INC4 citations73
US7961499B2Jun 14, 2011
Low leakage high performance static random access memory cell using dual-technology transistors
QUALCOMM INC5 citations73
US9911472B1Mar 6, 2018
Write bitline driver for a dual voltage domain
QUALCOMM INC2 citations72
US10050448B2Aug 14, 2018
Providing current cross-conduction protection in a power rail control system
QUALCOMM INC4 citations71
US9768779B2Sep 19, 2017
Voltage level shifters employing preconditioning circuits, and related systems and methods
QUALCOMM INC3 citations70
US9396794B1Jul 19, 2016
Matchline retention for mitigating search and write conflict
QUALCOMM INC3 citations70
US7725792B2May 25, 2010
Dual-path, multimode sequential storage element
QUALCOMM INC4 citations61
US9129706B2Sep 8, 2015
Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers
QUALCOMM INC3 citations60
US12265711B1Apr 1, 2025
Mechanism to enhance endurance in universal flash storage devices
QUALCOMM INC0 citations57
US12461859B2Nov 4, 2025
Interrupting memory access during background operations on a memory device
QUALCOMM INC0 citations49
US12271303B2Apr 8, 2025
System and method for updating memory tables
QUALCOMM INC0 citations49
US9666269B2May 30, 2017
Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods
QUALCOMM INC0 citations48
US12461669B2Nov 4, 2025
Memory device background operation management for low host battery
QUALCOMM INC0 citations47
US12417023B2Sep 16, 2025
Host device caching of flash memory address mappings
QUALCOMM INC0 citations47
US12341926B2Jun 24, 2025
Selective recording of multiuser calls
QUALCOMM INC0 citations47
US11593117B2Feb 28, 2023
Combining load or store instructions
QUALCOMM INC0 citations46
US10171080B2Jan 1, 2019
Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase
QUALCOMM INC0 citations42
US10559352B2Feb 11, 2020
Bitline-driven sense amplifier clocking scheme
QUALCOMM INC0 citations38
NXP BV
4 patentsUS7539879B2May 26, 2009
Register file gating to reduce microprocessor power dissipation
NXP BV54 citations95
US7500126B2Mar 3, 2009
Arrangement and method for controlling power modes of hardware resources
NXP BV46 citations94
US7577858B2Aug 18, 2009
Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device
NXP BV13 citations82
US7439759B2Oct 21, 2008
Operating long on-chip buses
NXP BV1 citations51
GARG MANISH
4 patentsUS8730713B2May 20, 2014
SRAM cell writability
GARG MANISH14 citations82
US8724373B2May 13, 2014
Apparatus for selective word-line boost on a memory cell
GARG MANISH16 citations82
US8239447B2Aug 7, 2012
Retrieving data using an asynchronous buffer
GARG MANISH3 citations52
US8576612B2Nov 5, 2013
Low leakage high performance static random access memory cell using dual-technology transistors
GARG MANISH0 citations51
CADENCE DESIGN SYSTEMS INC
3 patentsUS8875082B1Oct 28, 2014
System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data
CADENCE DESIGN SYSTEMS INC36 citations91
US11256837B1Feb 22, 2022
Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure
CADENCE DESIGN SYSTEMS INC2 citations63
US11494540B1Nov 8, 2022
Method, system, and computer program product for implementing electronic design closure with reduction techniques
CADENCE DESIGN SYSTEMS INC0 citations55
MICROSOFT TECHNOLOGY LICENSING LLC
3 patentsUS11126671B2Sep 21, 2021
Serializing plug-in data in a web page
MICROSOFT TECHNOLOGY LICENSING LLC3 citations71
US10491673B2Nov 26, 2019
Synchronization of conversation data
MICROSOFT TECHNOLOGY LICENSING LLC0 citations51
US9413703B2Aug 9, 2016
Synchronizing conversation structures in web-based email systems
MICROSOFT TECHNOLOGY LICENSING LLC0 citations51
ST MICROELECTRONICS INT NV
3 patentsUS11070198B2Jul 20, 2021
Loop independent differential hysteresis receiver
ST MICROELECTRONICS INT NV0 citations62
US11075624B2Jul 27, 2021
Hybrid driver having low output pad capacitance
ST MICROELECTRONICS INT NV0 citations51
US9331671B2May 3, 2016
Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods
ST MICROELECTRONICS INT NV0 citations39
LATTICE SEMICONDUCTOR CORP
2 patentsPHAN MICHAEL THAITHANH
2 patentsMORROW MICHAEL WILLIAM
1 patentBHAKAR GAUTAM
1 patentTOUSIGNANT PATRICK
1 patentCOUPANG CORP
1 patentTERECHKO ANDREI
1 patentFISCHER JEFFREY HERBERT
1 patentTEK AD OPUS INC
1 patentTVS MOTOR CO LTD
1 patentShowing the top 50 of 56 patents by PatentIndex Score.