P

Inventor

GARG MANISH

US56 patents
⚠️ This page may combine multiple inventors who share the name “GARG MANISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QUALCOMM INC

21 patents
US9870818B1Jan 16, 2018

Separate read and write address decoding in a memory system to support simultaneous memory read and write operations

QUALCOMM INC10 citations84
US8008961B2Aug 30, 2011

Adaptive clock generators, systems, and methods

QUALCOMM INC13 citations84
US9093125B2Jul 28, 2015

Low voltage write speed bitcell

QUALCOMM INC15 citations78
US8976618B1Mar 10, 2015

Decoded 2N-bit bitcells in memory for storing decoded bits, and related systems and methods

QUALCOMM INC4 citations73
US7961499B2Jun 14, 2011

Low leakage high performance static random access memory cell using dual-technology transistors

QUALCOMM INC5 citations73
US9911472B1Mar 6, 2018

Write bitline driver for a dual voltage domain

QUALCOMM INC2 citations72
US10050448B2Aug 14, 2018

Providing current cross-conduction protection in a power rail control system

QUALCOMM INC4 citations71
US9768779B2Sep 19, 2017

Voltage level shifters employing preconditioning circuits, and related systems and methods

QUALCOMM INC3 citations70
US9396794B1Jul 19, 2016

Matchline retention for mitigating search and write conflict

QUALCOMM INC3 citations70
US7725792B2May 25, 2010

Dual-path, multimode sequential storage element

QUALCOMM INC4 citations61
US9129706B2Sep 8, 2015

Dummy read to prevent crowbar current during read-write collisions in memory arrays with crosscoupled keepers

QUALCOMM INC3 citations60
US12265711B1Apr 1, 2025

Mechanism to enhance endurance in universal flash storage devices

QUALCOMM INC0 citations57
US12461859B2Nov 4, 2025

Interrupting memory access during background operations on a memory device

QUALCOMM INC0 citations49
US12271303B2Apr 8, 2025

System and method for updating memory tables

QUALCOMM INC0 citations49
US9666269B2May 30, 2017

Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods

QUALCOMM INC0 citations48
US12461669B2Nov 4, 2025

Memory device background operation management for low host battery

QUALCOMM INC0 citations47
US12417023B2Sep 16, 2025

Host device caching of flash memory address mappings

QUALCOMM INC0 citations47
US12341926B2Jun 24, 2025

Selective recording of multiuser calls

QUALCOMM INC0 citations47
US11593117B2Feb 28, 2023

Combining load or store instructions

QUALCOMM INC0 citations46
US10171080B2Jan 1, 2019

Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase

QUALCOMM INC0 citations42
US10559352B2Feb 11, 2020

Bitline-driven sense amplifier clocking scheme

QUALCOMM INC0 citations38

NXP BV

4 patents

GARG MANISH

4 patents

CADENCE DESIGN SYSTEMS INC

3 patents

MICROSOFT TECHNOLOGY LICENSING LLC

3 patents

ST MICROELECTRONICS INT NV

3 patents

LATTICE SEMICONDUCTOR CORP

2 patents

PHAN MICHAEL THAITHANH

2 patents

MORROW MICHAEL WILLIAM

1 patent

BHAKAR GAUTAM

1 patent

TOUSIGNANT PATRICK

1 patent

COUPANG CORP

1 patent

TERECHKO ANDREI

1 patent

FISCHER JEFFREY HERBERT

1 patent

TEK AD OPUS INC

1 patent

TVS MOTOR CO LTD

1 patent

Showing the top 50 of 56 patents by PatentIndex Score.