P

Inventor

FETTEROLF SHAWN P

US28 patents
⚠️ This page may combine multiple inventors who share the name “FETTEROLF SHAWN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

24 patents
US9947664B1Apr 17, 2018

Semiconductor device and method of forming the semiconductor device

IBM15 citations92
US10389519B2Aug 20, 2019

Hardware based cryptographic side-channel attack prevention

IBM8 citations84
US10607992B2Mar 31, 2020

Semiconductor device and method of forming the semiconductor device

IBM3 citations73
US10601404B2Mar 24, 2020

Contactless readable programmable transponder to monitor chip join

IBM2 citations73
US10200016B2Feb 5, 2019

Contactless readable programmable transponder to monitor chip join

IBM3 citations73
US9942761B1Apr 10, 2018

User access verification

IBM4 citations73
US9882005B2Jan 30, 2018

Fully depleted silicon-on-insulator device formation

IBM4 citations73
US9876487B2Jan 23, 2018

Contactless readable programmable transponder to monitor chip join

IBM2 citations73
US9786547B2Oct 10, 2017

Channel silicon germanium formation method

IBM2 citations72
US11569366B2Jan 31, 2023

Fully depleted SOI transistor with a buried ferroelectric layer in back-gate

IBM0 citations62
US11288429B2Mar 29, 2022

Electrical mask validation

IBM0 citations62
US11145677B2Oct 12, 2021

Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages

IBM0 citations62
US11075619B2Jul 27, 2021

Contactless readable programmable transponder to monitor chip join

IBM0 citations62
US11044606B2Jun 22, 2021

User access verification

IBM0 citations62
US10964648B2Mar 30, 2021

Chip security fingerprint

IBM0 citations62
US10921715B2Feb 16, 2021

Semiconductor structure for optical validation

IBM1 citations62
US10903332B2Jan 26, 2021

Fully depleted SOI transistor with a buried ferroelectric layer in back-gate

IBM1 citations62
US10650111B2May 12, 2020

Electrical mask validation

IBM1 citations62
US10559542B2Feb 11, 2020

Chip security fingerprint

IBM1 citations62
US10429743B2Oct 1, 2019

Optical mask validation

IBM1 citations62
US10629620B2Apr 21, 2020

Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages

IBM0 citations52
US10243046B2Mar 26, 2019

Fully depleted silicon-on-insulator device formation

IBM0 citations52
US9947747B2Apr 17, 2018

Fully depleted silicon-on-insulator device formation

IBM0 citations52
US10249529B2Apr 2, 2019

Channel silicon germanium formation method

IBM0 citations51

ANEMIKOS THEODOROS

2 patents

ELPIS TECH INC

1 patent

SAMSUNG ELECTRONICS CO LTD

1 patent