Inventor
HIETER NATHANIEL D
US14 patents
⚠️ This page may combine multiple inventors who share the name “HIETER NATHANIEL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
12 patentsUS10216875B2Feb 26, 2019
Leverage cycle stealing within optimization flows
IBM4 citations84
US9436791B1Sep 6, 2016
Optimizing placement of circuit resources using a globally accessible placement memory
IBM4 citations84
US9418188B1Aug 16, 2016
Optimizing placement of circuit resources using a globally accessible placement memory
IBM5 citations84
US7500207B2Mar 3, 2009
Influence-based circuit design
IBM9 citations83
US10552562B2Feb 4, 2020
Leverage cycle stealing within optimization flows
IBM1 citations73
US10540465B2Jan 21, 2020
Leverage cycle stealing within optimization flows
IBM1 citations73
US9747400B2Aug 29, 2017
Optimizing placement of circuit resources using a globally accessible placement memory
IBM2 citations73
US9703914B2Jul 11, 2017
Optimizing placement of circuit resources using a globally accessible placement memory
IBM2 citations73
US10970447B2Apr 6, 2021
Leverage cycle stealing within optimization flows
IBM0 citations62
US10210297B2Feb 19, 2019
Optimizing placement of circuit resources using a globally accessible placement memory
IBM0 citations52
US9785735B1Oct 10, 2017
Parallel incremental global routing
IBM1 citations50
US9639654B2May 2, 2017
Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit
IBM0 citations39