Inventor

WU JIANGANG

CN58 patents

⚠️ This page may combine multiple inventors who share the name “WU JIANGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU JIANGANG

MICRON TECHNOLOGY INC

Voltage bin selection for blocks of a memory device after power up of the memory device

Voltage bin selection for blocks of a memory device after power up of the memory device

Managing voltage bin selection for blocks of a memory device

Read counter for quality of service design

Multi-tier threshold voltage offset bin calibration

Memory access collision management on a shared wordline

Managing workload of programming sets of pages to memory device

Voltage calibration scans to reduce memory device overhead

Automatic wordline status bypass management

Multi-tier threshold voltage offset bin calibration

Voltage bin calibration based on a temporary voltage shift offset

Memory access collision management on a shared wordline

Selective partitioning of sets of pages programmed to memory device

Memory sub-system management of firmware block record and device block record

Memory compaction management in memory devices

Management of program suspend and resume operations of a memory sub-system

Granular error reporting on multi-pass programming of non-volatile memory

Managing voltage bin selection for blocks of a memory device

Memory sub-system logical block address remapping

Grouping blocks based on power cycle and power on time

Power loss data protection in a memory sub-system

Grouping blocks based on power cycle and power on time

Memory sub-system logical block address remapping

Power loss data protection in a memory sub-system

Coherency issue resolution in logical to physical page translation in a memory sub-system

Memory compaction management in memory devices

Performance control for a memory sub-system

Automatic wordline status bypass management

Memory sub-system write sequence track

Memory sub-system scan

Voltage calibration scans to reduce memory device overhead

Automatic wordline status bypass management

Performance control for a memory sub-system

Managing workload of programming sets of pages to memory device

Memory sub-system management of firmware block record and device block record

Memory sub-system write sequence track

Voltage bin calibration based on a temporary voltage shift offset

Memory die resource management

Memory sub-system scan

Performance control for a memory sub-system

Establishing a delay period associated with a program resume operation of a memory subsystem

Trims corresponding to program/erase cycles

Resource management for memory die-specific operations

Full multi-plane operation enablement

Selective accelerated sampling of failure- sensitive memory pages

ESPRESSIF SYS SHANGHAI CO LTD

Method and device for wireless transmission

Method and device for wireless transmission

LSI CORP

Read disturb handling in NAND flash

SPREADTRUM COMM SHANGHAI CO

Converting circuit with control circuit to detect signals input into the converting circuit, and communication device

EMERSON ELECTRIC CO

Stator assemblies for three phase dynamoelectric machines and related winding methods