Inventor

XU PENG

CN574 patents

⚠️ This page may combine multiple inventors who share the name “XU PENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XU PENG

IBM

Buffer regions for blocking unwanted diffusion in nanosheet transistors

Vertical field-effect transistor with uniform bottom spacer

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

Closely packed vertical transistors with reduced contact resistance

Transistor with air spacer and self-aligned contact

Forming a hybrid channel nanosheet semiconductor structure

Method of forming a nanosheet transistor

Inverse T-shaped contact structures having air gap spacers

Formation of stacked nanosheet semiconductor devices

Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor

Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

Nanosheet transistor

Tunnel transistor

Wrapped source/drain contacts with enhanced area

Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths

Vertical silicon/silicon-germanium transistors with multiple threshold voltages

Hybrid-channel nano-sheet FETs

Method and structure for improving vertical transistor

Forming on-chip metal-insulator-semiconductor capacitor

Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch

Approach to minimization of strain loss in strained fin field effect transistors

Multi-layer filled gate cut to prevent power rail shorting to gate structure

Multiple finFET formation with epitaxy separation

Forming fins utilizing alternating pattern of spacers

Vertical FET symmetric and asymmetric source/drain formation

Strained vertical field-effect transistor (FET) and method of forming the same

Transistor with asymmetric spacers

Vertical transistor with back bias and reduced parasitic capacitance

Method and structure for forming vertical transistors with shared gates and separate gates

Forming a sacrificial liner for dual channel devices

Reduced resistance source and drain extensions in vertical field effect transistors

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

KONINKL PHILIPS ELECTRONICS NV

Current control method and circuit for light emitting diodes

Supply assembly for a led lighting module

Single driver for multiple light emitting diodes

MITSUBISHI ELECTRIC RES LAB

Extraction of high-level features from low-level features of multimedia content

Method and system for high-level structure analysis and event detection in domain specific videos

MONOLITHIC POWER SYSTEMS INC

Switching regulator with automatic multi mode conversion

VIRGINIA TECH INTELL PROP

Multiphase clamp coupled-buck converter and magnetic integration

GOOGLE LLC

Encoding and adaptive, scalable accessing of distributed models

IMHOF MATTHIAS

Method for seismic interpretation using seismic texture attributes

WESTINGHOUSE ELECTRIC CORP

Deposition of integrated protective material into zirconium cladding for nuclear reactors by high-velocity thermal application

MEI TAO

User behavior model for contextual personalized recommendation

DONG YAN

Switching-mode power supply with ripple mode control and associated methods

THAYER IGNACIO E

Encoding and adaptive, scalable accessing of distributed models

WANG JINGBO

Automatic drilling advisory system based on correlation model and windowed principal component analysis

BRANTS THORSTEN

Large language models in machine translation

LSI CORP

Read disturb handling in NAND flash

GOOGLE INC

Discriminative training in machine learning

NIO ANHUI HOLDING CO LTD

Electronic device with graphical user interface