Inventor

PFIESTER JAMES R

US67 patents

Patents

50 patents

US5352631AOct 4, 1994

Method for forming a transistor having silicided regions

MOTOROLA INC172 citations99

US5182619AJan 26, 1993

Semiconductor device having an MOS transistor with overlapped and elevated source and drain

MOTOROLA INC170 citations99

US5241193AAug 31, 1993

Method for fabricating MOS transistors having gates with different work functions

MOTOROLA INC141 citations98

US4835112AMay 30, 1989

CMOS salicide process using germanium implantation

MOTOROLA INC132 citations97

US5426315AJun 20, 1995

Thin-film transistor having an inlaid thin-film channel region

MOTOROLA INC64 citations96

US5407847AApr 18, 1995

Method for fabricating a semiconductor device having a shallow doped region

MOTOROLA INC53 citations96

US5405806AApr 11, 1995

Method for forming a metal silicide interconnect in an integrated circuit

MOTOROLA INC58 citations96

US5371026ADec 6, 1994

Method for fabricating paired MOS transistors having a current-gain differential

MOTOROLA INC85 citations96

US5348903ASep 20, 1994

Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines

MOTOROLA INC70 citations96

US5334861AAug 2, 1994

Semiconductor memory cell

MOTOROLA INC74 citations96

US5200352AApr 6, 1993

Transistor having a lightly doped region and method of formation

MOTOROLA INC93 citations96

US5083190AJan 21, 1992

Shared gate CMOS transistor

MOTOROLA INC81 citations96

US5024959AJun 18, 1991

CMOS process using doped glass layer

MOTOROLA INC61 citations96

US5021354AJun 4, 1991

Process for manufacturing a semiconductor device

MOTOROLA INC71 citations96

US4978626ADec 18, 1990

LDD transistor process having doping sensitive endpoint etching

MOTOROLA INC83 citations96

US4948745AAug 14, 1990

Process for elevated source/drain field effect structure

MOTOROLA INC80 citations96

US4876213AOct 24, 1989

Salicided source/drain structure

MOTOROLA INC103 citations96

US4786611ANov 22, 1988

Adjusting threshold voltages by diffusion through refractory metal silicides

MOTOROLA INC60 citations96

US4714519ADec 22, 1987

Method for fabricating MOS transistors having gates with different work functions

MOTOROLA INC113 citations96

US5268590ADec 7, 1993

CMOS device and process

MOTOROLA INC70 citations95

US4928156AMay 22, 1990

N-channel MOS transistors having source/drain regions with germanium

MOTOROLA INC54 citations95

US4852062AJul 25, 1989

EPROM device using asymmetrical transistor characteristics

MOTOROLA INC98 citations95

US4728619AMar 1, 1988

Field implant process for CMOS using germanium

MOTOROLA INC88 citations95

US5616948AApr 1, 1997

Semiconductor device having electrically coupled transistors with a differential current gain

MOTOROLA INC26 citations93

US5536962AJul 16, 1996

Semiconductor device having a buried channel transistor

MOTOROLA INC32 citations93

US5373170ADec 13, 1994

Semiconductor memory device having a compact symmetrical layout

MOTOROLA INC52 citations93

US5371035ADec 6, 1994

Method for forming electrical isolation in an integrated circuit device

MOTOROLA INC39 citations93

US5330929AJul 19, 1994

Method of making a six transistor static random access memory cell

MOTOROLA INC45 citations93

US5324960AJun 28, 1994

Dual-transistor structure and method of formation

MOTOROLA INC37 citations93

US5319232AJun 7, 1994

Transistor having a lightly doped region

MOTOROLA INC45 citations93

US5264380ANov 23, 1993

Method of making an MOS transistor having improved transconductance and short channel characteristics

MOTOROLA INC42 citations93

US5047812ASep 10, 1991

Insulated gate field effect device

MOTOROLA INC28 citations93

US4997785AMar 5, 1991

Shared gate CMOS transistor

MOTOROLA INC38 citations93

US4992388AFeb 12, 1991

Short channel IGFET process

MOTOROLA INC27 citations93

US4988632AJan 29, 1991

Bipolar process using selective silicon deposition

MOTOROLA INC30 citations93

US4966864AOct 30, 1990

Contact structure and method

MOTOROLA INC45 citations93

US4948747AAug 14, 1990

Method of making an integrated circuit resistor

MOTOROLA INC36 citations93

US4918510AApr 17, 1990

Compact CMOS device structure

MOTOROLA INC37 citations93

US4847213AJul 11, 1989

Process for providing isolation between CMOS devices

MOTOROLA INC27 citations93

US4761385AAug 2, 1988

Forming a trench capacitor

MOTOROLA INC50 citations93

US5369052ANov 29, 1994

Method of forming dual field oxide isolation

MOTOROLA INC22 citations92

US5358890AOct 25, 1994

Process for fabricating isolation regions in a semiconductor device

MOTOROLA INC29 citations92

US5279976AJan 18, 1994

Method for fabricating a semiconductor device having a shallow doped region

MOTOROLA INC41 citations92

US5236862AAug 17, 1993

Method of forming oxide isolation

MOTOROLA INC26 citations92

US5082794AJan 21, 1992

Method of fabricating mos transistors using selective polysilicon deposition

MOTOROLA INC48 citations92

US4984042AJan 8, 1991

MOS transistors using selective polysilicon deposition

MOTOROLA INC22 citations92

US4837173AJun 6, 1989

N-channel MOS transistors having source/drain regions with germanium

MOTOROLA INC34 citations92

Showing the top 50 of 67 patents by PatentIndex Score.

PFIESTER JAMES R

Patents

Method for forming a transistor having silicided regions

Semiconductor device having an MOS transistor with overlapped and elevated source and drain

Semiconductor device having a thin-film transistor and process

Method for forming isolation regions in a semiconductor device

Process for fabricating a silicon on insulator field effect transistor

Method for fabricating MOS transistors having gates with different work functions

CMOS salicide process using germanium implantation

Thin-film transistor having an inlaid thin-film channel region

Method for fabricating a semiconductor device having a shallow doped region

Method for forming a metal silicide interconnect in an integrated circuit

Method for fabricating paired MOS transistors having a current-gain differential

Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines

Semiconductor memory cell

Transistor having a lightly doped region and method of formation

Shared gate CMOS transistor

CMOS process using doped glass layer

Process for manufacturing a semiconductor device

LDD transistor process having doping sensitive endpoint etching

Process for elevated source/drain field effect structure

Salicided source/drain structure

Adjusting threshold voltages by diffusion through refractory metal silicides

Method for fabricating MOS transistors having gates with different work functions

CMOS device and process

N-channel MOS transistors having source/drain regions with germanium

EPROM device using asymmetrical transistor characteristics

Field implant process for CMOS using germanium

Semiconductor device having electrically coupled transistors with a differential current gain

Semiconductor device having a buried channel transistor

Semiconductor memory device having a compact symmetrical layout

Method for forming electrical isolation in an integrated circuit device

Method of making a six transistor static random access memory cell

Dual-transistor structure and method of formation

Transistor having a lightly doped region

Method of making an MOS transistor having improved transconductance and short channel characteristics

Insulated gate field effect device

Shared gate CMOS transistor

Short channel IGFET process

Bipolar process using selective silicon deposition

Contact structure and method

Method of making an integrated circuit resistor

Compact CMOS device structure

Process for providing isolation between CMOS devices

Forming a trench capacitor

Method of forming dual field oxide isolation

Process for fabricating isolation regions in a semiconductor device

Method for fabricating a semiconductor device having a shallow doped region

Method of forming oxide isolation

Method of fabricating mos transistors using selective polysilicon deposition

MOS transistors using selective polysilicon deposition

N-channel MOS transistors having source/drain regions with germanium