Inventor
JENSEN MICHAEL GOTTLIEB
GB22 patents
⚠️ This page may combine multiple inventors who share the name “JENSEN MICHAEL GOTTLIEB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
18 patentsUS7634638B1Dec 15, 2009
Instruction encoding for system register bit set and clear
MIPS TECH INC61 citations98
US7149878B1Dec 12, 2006
Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
MIPS TECH INC85 citations97
US7664936B2Feb 16, 2010
Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
MIPS TECH INC26 citations92
US7660969B2Feb 9, 2010
Multithreading instruction scheduler employing thread group priorities
MIPS TECH INC17 citations92
US7657891B2Feb 2, 2010
Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
MIPS TECH INC18 citations92
US7558939B2Jul 7, 2009
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
MIPS TECH INC21 citations92
US7490230B2Feb 10, 2009
Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
MIPS TECH INC32 citations92
US7773621B2Aug 10, 2010
Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
MIPS TECH INC16 citations84
US7681014B2Mar 16, 2010
Multithreading instruction scheduler employing thread group priorities
MIPS TECH INC11 citations84
US7657883B2Feb 2, 2010
Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
MIPS TECH INC17 citations84
US7509447B2Mar 24, 2009
Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
MIPS TECH INC12 citations84
US7506140B2Mar 17, 2009
Return data selector employing barrel-incrementer-based round-robin apparatus
MIPS TECH INC18 citations84
US7925859B2Apr 12, 2011
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
MIPS TECH INC10 citations83
US7631130B2Dec 8, 2009
Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
MIPS TECH INC7 citations74
US7990989B2Aug 2, 2011
Transaction selector employing transaction queue group priorities in multi-port switch
MIPS TECH INC2 citations63
US7961745B2Jun 14, 2011
Bifurcated transaction selector supporting dynamic priorities in multi-port switch
MIPS TECH INC3 citations63
US7760748B2Jul 20, 2010
Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
MIPS TECH INC5 citations63
US7600100B2Oct 6, 2009
Instruction encoding for system register bit set and clear
MIPS TECH INC2 citations63