Inventor
IRRINKI V SWAMY
US20 patents
⚠️ This page may combine multiple inventors who share the name “IRRINKI V SWAMY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
19 patentsUS5784328AJul 21, 1998
Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
LSI LOGIC CORP209 citations98
US6367042B1Apr 2, 2002
Testing methodology for embedded memories using built-in self repair and identification circuitry
LSI LOGIC CORP170 citations97
US6067262AMay 23, 2000
Redundancy analysis for embedded memories with built-in self test and built-in self repair
LSI LOGIC CORP507 citations97
US6061814AMay 9, 2000
Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers
LSI LOGIC CORP135 citations97
US5987632ANov 16, 1999
Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations
LSI LOGIC CORP106 citations97
US5982659ANov 9, 1999
Memory cell capable of storing more than two logic states by using different via resistances
LSI LOGIC CORP128 citations97
US5956350ASep 21, 1999
Built in self repair for DRAMs using on-chip temperature sensing and heating
LSI LOGIC CORP91 citations97
US6255836B1Jul 3, 2001
Built-in self-test unit having a reconfigurable data retention test
LSI LOGIC CORP52 citations96
US6574762B1Jun 3, 2003
Use of a scan chain for configuration of BIST unit operation
LSI LOGIC CORP142 citations95
US6681358B1Jan 20, 2004
Parallel testing of a multiport memory
LSI LOGIC CORP67 citations93
US5867423AFeb 2, 1999
Memory circuit and method for multivalued logic storage by process variations
LSI LOGIC CORP25 citations92
US5822228AOct 13, 1998
Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits
LSI LOGIC CORP42 citations92
US5808932ASep 15, 1998
Memory system which enables storage and retrieval of more than two states in a memory cell
LSI LOGIC CORP39 citations92
US5761110AJun 2, 1998
Memory cell capable of storing more than two logic states by using programmable resistances
LSI LOGIC CORP34 citations92
US6757854B1Jun 29, 2004
Detecting faults in dual port FIFO memories
LSI LOGIC CORP46 citations91
US6671842B1Dec 30, 2003
Asynchronous bist for embedded multiport memories
LSI LOGIC CORP51 citations91
US6496950B1Dec 17, 2002
Testing content addressable static memories
LSI LOGIC CORP28 citations91
US5847990ADec 8, 1998
Ram cell capable of storing 3 logic states
LSI LOGIC CORP19 citations83
US6550032B1Apr 15, 2003
Detecting interport faults in multiport static memories
LSI LOGIC CORP18 citations82