P

Inventor

ZHANG BEI CHAO

SG24 patents
⚠️ This page may combine multiple inventors who share the name “ZHANG BEI CHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHARTERED SEMICONDUCTOR MFG

16 patents
US7524755B2Apr 28, 2009

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

CHARTERED SEMICONDUCTOR MFG37 citations91
US7012022B2Mar 14, 2006

Self-patterning of photo-active dielectric materials for interconnect isolation

CHARTERED SEMICONDUCTOR MFG7 citations73
US7803704B2Sep 28, 2010

Reliable interconnects

CHARTERED SEMICONDUCTOR MFG6 citations72
US6383922B1May 7, 2002

Thermal stability improvement of CoSi2 film by stuffing in titanium

CHARTERED SEMICONDUCTOR MFG8 citations72
US6517235B2Feb 11, 2003

Using refractory metal silicidation phase transition temperature points to control and/or calibrate RTP low temperature operation

CHARTERED SEMICONDUCTOR MFG9 citations64
US6995087B2Feb 7, 2006

Integrated circuit with simultaneous fabrication of dual damascene via and trench

CHARTERED SEMICONDUCTOR MFG4 citations62
US6967156B2Nov 22, 2005

Method to fabricate aligned dual damascene openings

CHARTERED SEMICONDUCTOR MFG3 citations62
US7781895B2Aug 24, 2010

Via electromigration improvement by changing the via bottom geometric profile

CHARTERED SEMICONDUCTOR MFG1 citations61
US7276440B2Oct 2, 2007

Method of fabrication of a die oxide ring

CHARTERED SEMICONDUCTOR MFG2 citations61
US7622403B2Nov 24, 2009

Semiconductor processing system with ultra low-K dielectric

CHARTERED SEMICONDUCTOR MFG2 citations60
US7294241B2Nov 13, 2007

Method to form alpha phase Ta and its application to IC manufacturing

CHARTERED SEMICONDUCTOR MFG3 citations57
US7678586B2Mar 16, 2010

Structure and method to prevent charge damage from e-beam curing process

CHARTERED SEMICONDUCTOR MFG0 citations52
US7947604B2May 24, 2011

Method for corrosion prevention during planarization

CHARTERED SEMICONDUCTOR MFG0 citations51
US7691739B2Apr 6, 2010

Via electromigration improvement by changing the via bottom geometric profile

CHARTERED SEMICONDUCTOR MFG0 citations51
US7372156B2May 13, 2008

Method to fabricate aligned dual damascene openings

CHARTERED SEMICONDUCTOR MFG0 citations51
US7256136B2Aug 14, 2007

Self-patterning of photo-active dielectric materials for interconnect isolation

CHARTERED SEMICONDUCTOR MFG0 citations51

GLOBALFOUNDRIES SG PTE LTD

2 patents

SEAH BOON MENG

1 patent

ZHANG SHAOQING

1 patent

ZHANG BEI CHAO

1 patent

DU LUYING

1 patent

SHENG HAIFENG

1 patent

HO VINCENT

1 patent