Inventor
LOONG SANG YEE
SG30 patents
⚠️ This page may combine multiple inventors who share the name “LOONG SANG YEE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
29 patentsUS6492726B1Dec 10, 2002
Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
CHARTERED SEMICONDUCTOR MFG267 citations99
US6252290B1Jun 26, 2001
Method to form, and structure of, a dual damascene interconnect device
CHARTERED SEMICONDUCTOR MFG123 citations98
US6611024B2Aug 26, 2003
Method of forming PID protection diode for SOI wafer
CHARTERED SEMICONDUCTOR MFG44 citations96
US6110787AAug 29, 2000
Method for fabricating a MOS device
CHARTERED SEMICONDUCTOR MFG99 citations96
US6261917B1Jul 17, 2001
High-K MOM capacitor
CHARTERED SEMICONDUCTOR MFG78 citations95
US6787422B2Sep 7, 2004
Method of body contact for SOI mosfet
CHARTERED SEMICONDUCTOR MFG20 citations93
US6376379B1Apr 23, 2002
Method of hard mask patterning
CHARTERED SEMICONDUCTOR MFG25 citations93
US6303414B1Oct 16, 2001
Method of forming PID protection diode for SOI wafer
CHARTERED SEMICONDUCTOR MFG42 citations93
US6284609B1Sep 4, 2001
Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions
CHARTERED SEMICONDUCTOR MFG22 citations92
US6248618B1Jun 19, 2001
Method of fabrication of dual gate oxides for CMOS devices
CHARTERED SEMICONDUCTOR MFG22 citations92
US7045455B2May 16, 2006
Via electromigration improvement by changing the via bottom geometric profile
CHARTERED SEMICONDUCTOR MFG17 citations91
US6406994B1Jun 18, 2002
Triple-layered low dielectric constant dielectric dual damascene approach
CHARTERED SEMICONDUCTOR MFG31 citations91
US6406948B1Jun 18, 2002
Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate
CHARTERED SEMICONDUCTOR MFG33 citations91
US6300172B1Oct 9, 2001
Method of field isolation in silicon-on-insulator technology
CHARTERED SEMICONDUCTOR MFG22 citations91
US6214680B1Apr 10, 2001
Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions
CHARTERED SEMICONDUCTOR MFG22 citations89
US6530380B1Mar 11, 2003
Method for selective oxide etching in pre-metal deposition
CHARTERED SEMICONDUCTOR MFG40 citations88
US6963113B2Nov 8, 2005
Method of body contact for SOI MOSFET
CHARTERED SEMICONDUCTOR MFG13 citations84
US6582856B1Jun 24, 2003
Simplified method of fabricating a rim phase shift mask
CHARTERED SEMICONDUCTOR MFG13 citations84
US6465296B1Oct 15, 2002
Vertical source/drain contact semiconductor
CHARTERED SEMICONDUCTOR MFG14 citations83
US6416909B1Jul 9, 2002
Alternating phase shift mask and method for fabricating the alignment monitor
CHARTERED SEMICONDUCTOR MFG16 citations81
US6653674B2Nov 25, 2003
Vertical source/drain contact semiconductor
CHARTERED SEMICONDUCTOR MFG11 citations73
US6764914B2Jul 20, 2004
Method of forming a high K metallic dielectric layer
CHARTERED SEMICONDUCTOR MFG6 citations72
US6492242B1Dec 10, 2002
Method of forming of high K metallic dielectric layer
CHARTERED SEMICONDUCTOR MFG8 citations72
US6486515B2Nov 26, 2002
ESD protection network used for SOI technology
CHARTERED SEMICONDUCTOR MFG9 citations72
US6495399B1Dec 17, 2002
Method of vacuum packaging a semiconductor device assembly
CHARTERED SEMICONDUCTOR MFG7 citations71
US6399431B1Jun 4, 2002
ESD protection device for SOI technology
CHARTERED SEMICONDUCTOR MFG3 citations63
US7781895B2Aug 24, 2010
Via electromigration improvement by changing the via bottom geometric profile
CHARTERED SEMICONDUCTOR MFG1 citations61
US7691739B2Apr 6, 2010
Via electromigration improvement by changing the via bottom geometric profile
CHARTERED SEMICONDUCTOR MFG0 citations51
US6737739B2May 18, 2004
Method of vacuum packaging a semiconductor device assembly
CHARTERED SEMICONDUCTOR MFG0 citations49