Inventor

GARCIA DAVID J

US39 patents

⚠️ This page may combine multiple inventors who share the name “GARCIA DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARCIA DAVID J

TANDEM COMPUTERS INC

Two level address translation and memory registration system and method

Detecting and isolating errors occurring in data communication in a multiple processor system

Method of management of a circular queue for asynchronous access

Network message routing using routing table information and supplemental enable information for deadlock prevention

Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source

Interrupt message delivery identified by storage location of received interrupt data

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Scan test apparatus for digital systems having dynamic random access memory

Method for verifying responses to messages using a barrier message

Method and apparatus for configuring routing paths of a network communicatively interconnecting a number of processing elements

Real time comparison of integrated circuit operation

Pseudo-Random scan test apparatus

Diagnostic apparatus for a data processing system

Clock synchronization system

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for implementing work request lists

Binding a memory window to a queue pair

System and method for configuring adaptive sets of links between routers in a system area network (SAN)

Memory window access mechanism

Method and system executing user programs on non-deterministic processors

Shared receive queues

Link extenders with error propagation and reporting

System and method for implementing multi-pathing data transfers in a system area network

Method and system of copying a memory area between processor elements for lock-step execution

Method and system of copying memory from a source processor to a target processor by duplicating memory writes

Method and system of determining whether a user program has made a system level call

Delegated write for race avoidance in a processor

COMPAQ COMPUTER CORP

Multiple processor system with standby sparing

Self-checked, lock step processor pairs

System and method for implementing error detection and recovery in a system area network

ARMSTRONG ROCKY E

Travel trailer stabilizer system

Travel trailer stabilizer system

ADAPTEC INC

Congestion management in a distributed computer system multiplying current variable injection rate with a constant to set new variable injection rate at source node

KRAUSE MICHAEL R

Reliable datagram transport service

COMPAQ INFORMATION TECHNOLOGIE

System and method for implementing multi-pathing data transfers in a system area network

TANDEM COMP INC

Method of data communication flow control in a data processing system using busy/ready commands

MOTOROLA INC

Utilizing a portable electronic device to detect motion

US GOV AIR FORCE

Deployable origami structure

BRUCKERT WILLIAM F

Method and system of exchanging information between processors

HILLAND JEFFREY

Protection domain groups to isolate access to memory windows